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Enhanced I/O Flash Type MCU
HT68F13/HT68F14/HT68F15
Revision: 1.00
Date: February 9, 2011
Contents
Table of Contents
Features ...............................................................................................6
CPU Features ........................................................................................................6 Peripheral Features ................................................................................................6
General Description ............................................................................6 Selection Table ....................................................................................7 Block Diagram .....................................................................................7 Pin Assignment ...................................................................................8 Pin Description ....................................................................................9
HT68F13 ................................................................................................................9 HT68F14 ..............................................................................................................10 HT68F15 ..............................................................................................................11
Absolute Maximum Ratings .............................................................12 D.C. Characteristics ..........................................................................12 A.C. Characteristics ..........................................................................14 Power-on Reset Characteristics ......................................................15 System Architecture .........................................................................16
Clocking and Pipelining ........................................................................................16 Program Counter..................................................................................................17 Stack ....................................................................................................................17 Arithmetic and Logic Unit - ALU ...........................................................................18
Flash Program Memory ....................................................................19
Structure...............................................................................................................19 Special Vectors.....................................................................................................19 Look-up Table.......................................................................................................19 Table Program Example .......................................................................................20 In Circuit Programming.........................................................................................21
RAM Data Memory.............................................................................22
Structure...............................................................................................................22
Rev. 1.10
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February 9, 2011
Contents
Special Function Register Description ...........................................24
Indirect Addressing Registers - IAR0, IAR1..........................................................24 Memory Pointers - MP0, MP1 ..............................................................................24 Accumulator - ACC ..............................................................................................25 Program Counter Low Register - PCL..................................................................25 Look-up Table Registers - TBLP, TBHP, TBLH.....................................................25 Status Register - STATUS ...................................................................................25
Oscillator............................................................................................27
Oscillator Overview...............................................................................................27 System Clock Configurations................................................................................27 External Crystal/ Ceramic Oscillator - HXT ..........................................................28 External RC Oscillator - ERC ...............................................................................29 Internal RC Oscillator - HIRC ...............................................................................29 Internal 32kHz Oscillator - LIRC...........................................................................29 Supplementary Oscillator......................................................................................29
Operating Modes and System Clocks .............................................30
System Clocks......................................................................................................30 System Operation Modes .....................................................................................30 Control Register ...................................................................................................32 Fast Wake-up .......................................................................................................33
Operating Mode Switching ...............................................................34
NORMAL Mode to SLOW Mode Switching...........................................................35 SLOW Mode to NORMAL Mode Switching...........................................................36 Entering the SLEEP0 Mode................................................................................37 Entering the SLEEP1 Mode..................................................................................37 Entering the IDLE0 Mode .....................................................................................37 Entering the IDLE1 Mode .....................................................................................38 Standby Current Considerations...........................................................................38 Wake-up...............................................................................................................38 Programming Considerations ...............................................................................39
Watchdog Timer ................................................................................39
Watchdog Timer Clock Source .............................................................................39 Watchdog Timer Control Register.........................................................................40 Watchdog Timer Operation...................................................................................40
Reset and Initialisation .....................................................................42
Reset Functions ...................................................................................................42 Reset Initial Conditions .........................................................................................45
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February 9, 2011
Contents
Input/Output Ports.............................................................................51
I/O Register List....................................................................................................51 Pull-high Resistors................................................................................................53 Port A Wake-up ....................................................................................................54 I/O Port Control Registers.....................................................................................54 I/O Pin Structures .................................................................................................56 Programming Considerations ...............................................................................56
Timer Modules - TM...........................................................................57
Introduction ..........................................................................................................57 TM Operation .......................................................................................................58 TM Clock Source..................................................................................................58 TM Interrupts ........................................................................................................58 TM External Pins ..................................................................................................58 TM Input/Output Pin Control Registers .................................................................59 Programming Considerations ...............................................................................64
Compact Type TM - CTM...................................................................65
Compact TM Operation ........................................................................................65 Compact Type TM Register Description ...............................................................66 Compact Type TM Operating Modes ....................................................................70
Standard Type TM - STM...................................................................75
Standard TM Operation ........................................................................................75 Standard Type TM Register Description ...............................................................76 Standard Type TM Operating Modes....................................................................80
Enhanced Type TM - ETM .................................................................87
Enhanced TM Operation ......................................................................................87 Enhanced Type TM Register Description..............................................................88 Enhanced Type TM Operating Modes ..................................................................93 Compare Output Mode .........................................................................................94 Capture Input Mode............................................................................................105
Interrupts..........................................................................................107
Interrupt Registers ..............................................................................................107 Interrupt Operation..............................................................................................112 External Interrupt ................................................................................................114 Multi-function Interrupt ........................................................................................115 Time Base Interrupts...........................................................................................115 LVD Interrupt ......................................................................................................116 TM Interrupts ......................................................................................................116 Interrupt Wake-up Function.................................................................................117 Programming Considerations .............................................................................117
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Contents
Power Down Mode and Wake-up ...................................................118
Entering the IDLE or SLEEP Mode .....................................................................118 Standby Current Considerations .........................................................................118 Wake-up .............................................................................................................118
Low Voltage Detector - LVD ............................................................119
LVD Register ......................................................................................................119 LVD Operation....................................................................................................120
SCOM Function for LCD .................................................................120
LCD Operation ...................................................................................................120 LCD Bias Control................................................................................................121
Configuration Options ....................................................................122 Application Circuits ........................................................................122 Instruction Set .................................................................................123
Introduction.........................................................................................................123 Instruction Timing ...............................................................................................123 Moving and Transferring Data ............................................................................123 Arithmetic Operations .........................................................................................123 Logical and Rotate Operations ...........................................................................123 Branches and Control Transfer...........................................................................124 Bit Operations.....................................................................................................124 Table Read Operations.......................................................................................124 Other Operations................................................................................................124 Instruction Set Summary ....................................................................................125
Instruction Definition ......................................................................127 Package Information .......................................................................137
16-pin DIP (300mil) Outline Dimensions .............................................................137 16-pin NSOP (150mil) Outline Dimensions .........................................................140 16-pin SSOP (150mil) Outline Dimensions .........................................................141 20-pin DIP (300mil) Outline Dimensions .............................................................142 20-pin SOP (300mil) Outline Dimensions............................................................144 20-pin SSOP (150mil) Outline Dimensions .........................................................145 24-pin SKDIP (300mil) Outline Dimensions ........................................................146 24-pin SOP (300mil) Outline Dimensions............................................................149 24-pin SSOP (150mil) Outline Dimensions .........................................................150 28-pin SKDIP (300mil) Outline Dimensions ........................................................151 28-pin SOP (300mil) Outline Dimensions............................................................152 28-pin SSOP (150mil) Outline Dimensions .........................................................153 Reel Dimensions ................................................................................................154 Carrier Tape Dimensions ....................................................................................156
Rev. 1.10
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February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Features
CPU Features
*
* * *
* * * * * * *
Operating Voltage: fSYS= 8MHz: 2.2V~5.5V fSYS= 12MHz: 2.7V~5.5V fSYS= 20MHz: 4.5V~5.5V Up to 0.2ms instruction cycle with 20MHz system clock at VDD=5V Power down and wake-up functions to reduce power consumption Four oscillators: External Crystal -- HXT External RC -- ERC Internal RC -- HIRC Internal 32kHz RC -- LIRC Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP Fully integrated internal 4MHz, 8MHz and 12MHz oscillator requires no external components All instructions executed in one or two instruction cycles Table read instructions 63 powerful instructions Up to 8-level subroutine nesting Bit manipulation instruction
Peripheral Features
* * * * * * * * * * *
Flash Program Memory: 1K14 ~ 4K15 RAM Data Memory: 648 ~ 1928 Watchdog Timer function Up to 26 bidirectional I/O lines Software controlled 4-SCOM lines LCD driver with 1/2 bias Multiple pin-shared external interrupts Multiple Timer Module for time measure, input capture, compare match output, PWM output or single pulse output function Single Time-Base function for generation of fixed time interrupt signal Low voltage reset function Low voltage detect function Wide range of available package types
General Description
The HT68F1x series of devices are Flash Memory I/O type 8-bit high performance RISC architecture microcontrollers. Offering users the convenience of Flash Memory multi-programming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory for application program data storage. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HXT, ERC, HIRC and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption.
Rev. 1.10
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February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
The inclusion of flexible I/O programming features, Time-Base functions along with many other features ensure that the devices will find excellent use in applications such as electronic metering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others.
Selection Table
Most features are common to all devices, the main feature distinguishing them are Memory capacity, I/O count, TM features, stack capacity and package types. The following table summarises the main features of each device.
Part No. HT68F13 VDD 2.2V~ 5.5V 2.2V~ 5.5V 2.2V~ 5.5V Program Memory 1K14 Data Memory 648 I/O 18 Ext. Int. 2 Timer Module 10-bit STM1 10-bit CTM1 10-bit STM1 10-bit CTM1 10-bit ETM1 Stack 4 Package 16DIP/NSOP/SSOP 20DIP/SOP/SSOP 16DIP/NSOP/SSOP 20DIP/SOP/SSOP 24SKDIP/SOP/SSOP 16DIP/NSOP/SSOP 20DIP/SOP/SSOP 24/28SKDIP/SOP/SSOP
HT68F14
2K15
968
22
2
4
HT68F15 Note:
4K15
1288
26
2
8
As devices exist in more than one package format, the table reflects the situation for the package with the most pins.
Block Diagram
Low V o lta g e D e te c t F la s h M e m o r y P r o g r a m m in g C ir c u itr y ( IC P ) F la s h P ro g ra m M e m o ry Low V o lta g e R eset RAM D a ta M e m o ry W a tc h d o g T im e r R eset C ir c u it 8 - b it R IS C MCU C o re In te rru p t C o n tr o lle r E R C /H X T O s c illa to r
T im e B ase
H IR C O s c illa to r I/O TM 0 TM 1
L IR C O s c illa to r
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February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Pin Assignment
PA0 PA0 PA1 PA2 PA3 PA4 P A 6 /T C K 1 7 8 PA5 5 6 4 3 2 1 16 15 14 13 12 11 10 9 PB0 VSS P B 1 /O S C 1 P B 2 /O S C 2 VDD P B 3 /R E S PA1 PA2 PA3 PA4 P A 6 /T C K 1 PA5 6 7 8 9 10 5 4 3 2 1 20 19 18 17 16 15 14 13 12 11 PB0 VSS P B 1 /O S C 1 P B 2 /O S C 2 VDD P B 3 /R E S
P A 7 /T P 1 _ 0
P B 4 /IN T 0 P B 5 /IN T 1
P C 1 /S C O M 1 P C 0 /S C O M 0
P A 7 /T P 1 _ 0
P B 4 /IN T 0 P B 5 /IN T 1 P B 6 /T P 1 _ 1 /S C O M 2 P B 7 /S C O M 3
H T68F13 1 6 D IP -A /N S O P -A /S S O P -A
H T68F13 2 0 D IP -A /S O P -A /S S O P -A PA0 PA0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PB0 VSS P B 1 /O S C 1 P B 2 /O S C 2 VDD P B 3 /R E S PA1 PA2 P A 4 /T C K 0 P A 6 /T C K 1 PA3 4 5 6 7 8 9 10 11 12 3 2 1 24 23 22 21 20 19 18 17 16 15 14 13 PB0 VSS P B 1 /O S C 1 P B 2 /O S C 2 VDD P B 3 /R E S
PA0 PA1 PA2 P A 4 /T C K 0 5 6 7 8 P A 6 /T C K 1 PA3 3 4 2 1
16 15 14 13 12 11 10 9
PB0 VSS P B 1 /O S C 1 P B 2 /O S C 2 VDD P B 3 /R E S
PA1 PA2 P A 4 /T C K 0 P A 6 /T C K 1 PA3
P A 5 /T P 0 _ 0 P A 7 /T P 1 _ 0
P A 5 /T P 0 _ 0 P A 7 /T P 1 _ 0
P B 4 /IN T 0 P B 5 /IN T 1 PD0 PD1
P A 5 /T P 0 _ 0 P A 7 /T P 1 _ 0
P B 4 /IN T 0 P B 5 /IN T 1 P B 6 /T P 1 _ 1 /S C O M 2 P B 7 /S C O M 3
PC3 PC2
P B 4 /IN T 0 P B 5 /IN T 1
P C 1 /T P 0 _ 1 /S C O M 1 P C 0 /S C O M 0
P C 1 /T P 0 _ 1 /S C O M 1 P C 0 /S C O M 0
P B 6 /T P 1 _ 1 /S C O M 2 P B 7 /S C O M 3
H T68F14 1 6 D IP -A /N S O P -A /S S O P -A
H T68F14 2 0 D IP -A /S O P -A /S S O P -A
H T68F14 2 4 S K D IP -A /S O P -A /S S O P -A PA0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 PB0 VSS P B 1 /O S C 1 P B 2 /O S C 2 VDD P B 3 /R E S
PA0 P B 2 /O S C 2 P B 1 /O S C 1 VSS 2 3 4 5 6 7 8 PB0 PA0 PA1 PA3 PA2 1 16 15 14 13 12 11 10 9 VDD PA1 PA2 P A 4 /T C K 0 P A 6 /T C K 1 PA3 5 6 7 8 9 4 3 2
1
20 19 18 17 16 15 14 13 10 12 11
PB0 VSS P B 1 /O S C 1 P B 2 /O S C 2 VDD P B 3 /R E S
PA1 PA2 P A 4 /T C K 0 P A 6 /T C K 1 PA3
P B 4 /IN T 0 P B 5 /IN T 1 P B 3 /R E S P A 5 /T P 0 _ 0 P A 6 /T C K 1 P A 4 /T C K 0
P A 5 /T P 0 _ 0 P A 7 /T P 1 B _ 0
P A 5 /T P 0 _ 0
P B 4 /IN T 0 P B 5 /IN T 1 PD0 PD1
P A 7 /T P 1 B _ 0
P C 1 /T P 0 _ 1 /S C O M 1 P C 0 /T P 1 A /S C O M 0
P A 7 /T P 1 B _ 0
P B 4 /IN T 0 P B 5 /IN T 1 P B 6 /T P 1 B _ 1 /S C O M 2 P B 7 /T P 1 B _ 2 /S C O M 3
PC3 PC2
P C 1 /T P 0 _ 1 /S C O M 1 P C 0 /T P 1 A /S C O M 0
P B 6 /T P 1 B _ 1 /S C O M 2 P B 7 /T P 1 B _ 2 /S C O M 3
H T68F15 1 6 D IP -A /N S O P -A /S S O P -A
H T68F15 2 0 D IP -A /S O P -A /S S O P -A
H T68F15 2 4 S K D IP -A /S O P -A /S S O P -A
PA0 PA1 PA2 P A 4 /T C K 0 P A 6 /T C K 1 PA3 4 5 6 7 8 9 3 2 1
28 27 26 25 24 23 22 21 10 11 12 13 14 20 19 18 17 16 15
PB0 VSS P B 1 /O S C 1 P B 2 /O S C 2 VDD P B 3 /R E S
P A 5 /T P 0 _ 0
P A 7 /T P 1 B _ 0
P B 4 /IN T 0 P B 5 /IN T 1 PC6 PC7 PD0 PD1 P B 6 /T P 1 B _ 1 /S C O M 2 P B 7 /T P 1 B _ 2 /S C O M 3
PC5 PC4 PC3 PC2
P C 1 /T P 0 _ 1 /S C O M 1 P C 0 /T P 1 A /S C O M 0
H T68F15 2 8 S K D IP -A /S O P -A /S S O P -A
Rev. 1.10
8
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Pin Description
With the exception of the power pins, all pins on these devices can be referenced by their Port name, e.g. PA.0, PA.1 etc, which refer to the digital I/O function of the pins. However some of these Port pins are also shared with other function such as the Analog to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet.
HT68F13
Pin Name PA0~PA7 PB0~PB7 PC0~PC1 TCK1 TP1_0, TP1_1 INT0, INT1 SCOM0~SCOM3 OSC1 OSC2 RES VDD VSS Note: Port A Port B Port C TM1 input TM1 I/O Ext. Interrupt 0, 1 SCOM0~SCOM3 HXT/ERC pin HXT pin Reset pin Power supply * Ground * Function OP PAWU PAPU PBPU PCPU 3/4 TMPC 3/4 SCOMC CO CO CO 3/4 3/4 I/T ST ST ST ST ST ST 3/4 HXT 3/4 ST PWR PWR O/T CMOS CMOS CMOS 3/4 CMOS 3/4 SCOM 3/4 HXT 3/4 3/4 3/4 Pin-Shared Mapping 3/4 3/4 3/4 PA6 PA7, PB6 PB4, PB5 PC0, PC1, PB6, PB7 PB1 PB2 PB3 3/4 3/4
I/T: Input type O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power CO: Configuration option ST: Schmitt Trigger input CMOS: CMOS output SCOM: Software controlled LCD COM HXT: High frequency crystal oscillator
Rev. 1.10
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February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
HT68F14
Pin Name PA0~PA7 PB0~PB7 PC0~PC3 PD0~PD1 TCK0, TCK1 TP0_0, TP0_1 TP1_0, TP1_1 INT0, INT1 SCOM0~SCOM3 OSC1 OSC2 RES VDD VSS Note: Port A Port B Port C Port D TM0, TM1 input TM0 I/O TM1 I/O Ext. Interrupt 0, 1 SCOM0~SCOM3 HXT/ERC pin HXT pin Reset pin Power supply * Ground * Function OP PAWU PAPU PBPU PCPU PDPU 3/4 TMPC TMPC 3/4 SCOMC CO CO CO 3/4 3/4 I/T ST ST ST ST ST ST ST ST 3/4 HXT 3/4 ST PWR PWR O/T CMOS CMOS CMOS CMOS 3/4 CMOS CMOS 3/4 SCOM 3/4 HXT 3/4 3/4 3/4 Pin-Shared Mapping 3/4 3/4 3/4 3/4 PA4, PA6 PA5, PC1 PA7, PB6 PB4, PB5 PC0, PC1, PB6, PB7 PB1 PB2 PB3 3/4 3/4
I/T: Input type I/T: Input type O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power CO: Configuration option ST: Schmitt Trigger input CMOS: CMOS output SCOM: Software controlled LCD COM HXT: High frequency crystal oscillator
Rev. 1.10
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February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
HT68F15
Pin Name PA0~PA7 PB0~PB7 PC0~PC7 PD0~PD1 TCK0, TCK1 TP0_0, TP0_1 TP1A Port A Port B Port C Port D TM0, TM1 input TM0 I/O TM1 I/O Function OP PAWU PAPU PBPU PCPU PDPU 3/4 TMPC TMPC TMPC 3/4 SCOMC CO CO CO 3/4 3/4 I/T ST ST ST ST ST ST ST ST ST 3/4 HXT 3/4 ST PWR PWR O/T CMOS CMOS CMOS CMOS 3/4 CMOS CMOS CMOS 3/4 SCOM 3/4 HXT 3/4 3/4 3/4 Pin-Shared Mapping 3/4 3/4 3/4 3/4 PA4, PA6 PA5, PC1 PC0 PA7, PB6, PB7 PB4, PB5 PC0, PC1, PB6, PB7 PB1 PB2 PB3 3/4 3/4
TP1B_0, TP1B_1, TM1 I/O TP1B_2 INT0, INT1 SCOM0~SCOM3 OSC1 OSC2 RES VDD VSS Note: Ext. Interrupt 0, 1 SCOM0~SCOM3 HXT/ERC pin HXT pin Reset pin Power supply * Ground *
I/T: Input type O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power CO: Configuration option ST: Schmitt Trigger input CMOS: CMOS output SCOM: Software controlled LCD COM HXT: High frequency crystal oscillator
Rev. 1.10
11
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Absolute Maximum Ratings
Supply Voltage ...............................................................................................VSS-0.3V to VSS+6.0V Input Voltage .................................................................................................VSS-0.3V to VDD+0.3V Storage Temperature .................................................................................................-50C to 125C Operating Temperature................................................................................................-40C to 85C IOL Total...................................................................................................................................100mA IOH Total ................................................................................................................................-100mA Total Power Dissipation .........................................................................................................500mW Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Test Conditions Symbol Parameter VDD Operating Voltage (HXT, ERC, HIRC) Conditions fSYS=8MHz VDD 3/4 fSYS=12MHz fSYS=20MHz 3V 5V IDD1 Operating Current, Normal Mode, fSYS=fH (HXT, ERC, HIRC) 3V 5V 3V 5V IDD2 Operating Current, Normal Mode, fSYS=fH (HXT) Operating Current, Slow Mode, fSYS=fL (LIRC) IDLE0 Mode Standby Current (LIRC on) IDLE1 Mode Standby Current (HXT, ERC, HIRC) SLEEP0 Mode Standby Current (LIRC off) SLEEP1 Mode Standby Current (LIRC on) Input Low Voltage for I/O Ports or Input Pins except RES pin 5V 3V 5V 3V No load, WDT enable 5V 3V 5V 3V No load, WDT disable 5V 3V No load, WDT enable 5V 3/4 5V 3/4 3/4 No load, WDT enable, fSYS=12MHz on No load, fSYS=fH=4MHz, WDT enable No load, fSYS=fH=8MHz, WDT enable No load, fSYS=fH=12MHz, WDT enable No load, fSYS=fH=20MHz, WDT enable No load, fSYS=fL, WDT enable 2.2 2.7 4.5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0 3/4 3/4 3/4 0.7 1.8 1.6 3.3 2.2 5.0 6.0 10 30 1.5 3.0 0.55 1.30 3/4 3/4 1.5 2.5 3/4 3/4 5.5 5.5 5.5 1.1 2.7 2.4 5.0 3.3 7.5 9.0 20 50 3.0 6.0 0.83 2.00 1 2 3.0 5.0 0.2VDD 1.5 Min. Typ. Max.
Ta=25C
Unit V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V
IDD3
IIDLE0
IIDLE1
ISLEEP0
ISLEEP1
VIL1
Rev. 1.10
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February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Test Conditions Symbol Parameter VDD VIH1 VIL2 VIH2 Input High Voltage for I/O Ports or Input Pins except RES pin Input Low Voltage (RES) Input High Voltage (RES) 3/4 5V 3/4 3/4 Conditions 3/4 3/4 3/4 3/4 LVR Enable, 2.10V option VLVR LVR Voltage Level 3/4 LVR Enable, 2.55V option LVR Enable, 3.15V option LVR Enable, 4.20V option LVDEN=1, VLVD=2.0V LVDEN=1, VLVD=2.2V LVDEN=1, VLVD=2.4V VLVD LVD Voltage Level 3/4 LVDEN=1, VLVD=2.7V LVDEN=1, VLVD=3.0V LVDEN=1, VLVD=3.3V LVDEN=1, VLVD=3.6V LVDEN=1, VLVD=4.4V LVR Enable, LVDEN=0 ILV Additional Power Consumption if LVR and LVD is Used 3/4 LVR disable, LVDEN=1 LVR enable, LVDEN=1 3V VOL Output Low Voltage I/O Port 5V 3V VOH Output High Voltage I/O Port 5V RPH Pull-high Resistance for I/O Ports 3V 5V IOL=20mA IOH=-3.2mA IOH=-7.4mA 3/4 SCOMC, ISEL[1:0]=00 SCOMC, ISEL[1:0]=01 ISCOM SCOM Operating Current 5V SCOMC, ISEL[1:0]=10 SCOMC, ISEL[1:0]=11 VSCOM VDD/2 Voltage for LCD COM 5V No load 70 140 0.475 100 200 0.500 130 260 0.525 IOL=9mA 0.8VDD 3.5 0 0.9VDD -5% -5% -5% -5% -5% -5% -5% -5% -5% -5% -5% -5% 3/4 3/4 3/4 3/4 3/4 2.7 4.5 20 10 17.5 35 3/4 3/4 3/4 3/4 2.10 2.55 3.15 4.20 2.00 2.20 2.40 2.70 3.00 3.30 3.60 4.40 60 75 90 3/4 3/4 3/4 3/4 60 30 25.0 50 VDD 5.0 0.4VDD VDD +5% +5% +5% +5% +5% +5% +5% +5% +5% +5% +5% +5% 90 115 135 0.3 0.5 3/4 3/4 100 50 32.5 65 V V V V V V V V V V V V V V V V mA mA mA V V V V kW kW mA mA mA mA VDD Min. Typ. Max. Unit
Rev. 1.10
13
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
A.C. Characteristics
Test Conditions Symbol Parameter VDD Conditions 2.2V~5.5V fCPU Operating Clock 3/4 2.7V~5.5V 4.5V~5.5V 2.2V~5.5V fSYS System Clock (HXT) 3/4 2.7V~5.5V 4.5V~5.5V 3V/5V Ta=25C 3V/5V Ta=25C 5V Ta=25C DC DC DC 0.4 0.4 0.4 -2% -2% -2% -5% -4% -5% -7% -5% -6% -4% -6% -12% -10% -15% -8% -12% -2% -5% -7% -9% -15% 3/4 3/4 3/4 3/4 3/4 3/4 4 8 12 4 8 12 4 4 8 8 12 4 4 8 8 12 8 8 8 8 8 8 12 20 8 12 20 +2% +2% +2% +5% +4% +3% +7% +9% +4% +9% +7% +8% +9% +4% +9% +7% +2% +6% +9% +10% +10% MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Min. Typ. Max. Unit Ta=25C
3V/5V Ta=0~70C 3V/5V Ta=0~70C 5V Ta=0~70C
2.2V~ Ta=0~70C 3.6V 3.0V~ Ta=0~70C 5.5V 2.2V~ Ta=0~70C 3.6V 3.0V~ Ta=0~70C 5.5V 3.0V~ Ta=0~70C 5.5V 2.2V~ Ta= -40C~85C 3.6V 3.0V~ Ta= -40C~85C 5.5V 2.2V~ Ta= -40C~85C 3.6V 3.0V~ Ta= -40C~85C 5.5V 3.0V~ Ta= -40C~85C 5.5V 5V 5V 5V fERC System Clock (ERC) Ta=25C, R=120kW * Ta=0~70C, R=120kW * Ta= -40C~85C, R=120kW *
fHIRC
System Clock (HIRC)
3.0V~ Ta= -40C~85C, 5.5V R=120kW * 2.2V~ Ta= -40C~85C, 5.5V R=120kW *
Rev. 1.10
14
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Test Conditions Symbol Parameter VDD 5V fLIRC System Clock (LIRC) Conditions 3/4 -10% -50% 3/4 1 1 120 20 15 200 3/4 3/4 3/4 32 32 3/4 3/4 3/4 240 45 3/4 3/4 1024 15~16 1~2 +10% +60% 1 3/4 3/4 480 90 3/4 3/4 3/4 3/4 3/4 tSYS kHz kHz fSYS ms tSYS ms ms ms ms Min. Typ. Max. Unit
2.2V~ Ta=-40C~+85C 5.5V 3/4 3/4 3/4 3/4 3/4 3/4 3/4 fSYS=HXT 3/4 3/4 3/4 3/4 3/4 3/4 3/4
fTIMER tRES tINT tLVR tLVD tLVDS tBGS
Timer Input Pin Frequency External Reset Low Pulse Width Interrupt Pulse Width Low Voltage Width to Reset Low Voltage Width to Interrupt LVDO stable time VBG Turn on Stable Time
tSST
System Start-up Timer Period (Wake-up from HALT)
3/4
fSYS=ERC or HIRC fSYS=LIRC OSC
Note:
1. tSYS=1/fSYS 2. * For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended. 3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible.
Power-on Reset Characteristics
Test Conditions Symbol Parameter VDD VPOR RRVDD tPOR VDD Start Voltage to Ensure Power-on Reset VDD Raising Rate to Ensure Power-on Reset Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset 3/4 3/4 3/4 Conditions 3/4 3/4 3/4 3/4 0.035 1 3/4 3/4 3/4 100 3/4 3/4 Min. Typ. Max.
Ta=25C
Unit
mV V/ms ms
V
DD
tP
OR
RR
VDD
V
POR
T im e
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System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications.
Clocking and Pipelining
The main system clock, derived from either a HXT, ERC, HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.
(S y s te m fS Y S C lo c k )
P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r PC F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 ) PC+1 PC+2
P ip e lin in g
F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1 2 3 4 5 6 D ELAY: : :
M O V A ,[1 2 H ] C ALL D ELAY C P L [1 2 H ] NOP
F e tc h In s t. 1
E x e c u te In s t. 1 F e tc h In s t. 2
E x e c u te In s t. 2 F e tc h In s t. 3
F lu s h P ip e lin e F e tc h In s t. 6
E x e c u te In s t. 6 F e tc h In s t. 7
Instruction Fetching
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For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
Program Counter
During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as JMP or CALL that demand a jump to a non-consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
Program Counter Device HT68F13 HT68F14 HT68F15 Program Counter High Byte PC9, PC8 PC10~PC8 PC11~PC8 Program Counter PCL7~PCL0 Low Byte (PCL Register)
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch.
Stack
This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching.
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If the stack is overflow, the first Program Counter save in the stack will be lost.
P ro g ra m C o u n te r
T o p o f S ta c k S ta c k P o in te r
S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k L e v e l 3 P ro g ra m M e m o ry
B o tto m
o f S ta c k
S ta c k L e v e l N
Device HT68F13 HT68F14 HT68F15
Stack Levels 4 4 8
Arithmetic and Logic Unit - ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:
* * * * *
Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA Logic operations: AND, OR, XOR, , ORM, XORM, CPL, CPLA Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC Increment and Decrement INCA, INC, DECA, DEC Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
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Flash Program Memory
The Program Memory is the location where the user code or program is stored. For this device series the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating.
Structure
The Program Memory has a capacity of 1K14 bits to 4K15 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register.
Device HT68F20 HT68F30 HT68F40
H T68F13 0000H 0004H 001CH 03FFH R eset In te rru p t V e c to r 1 4 b its 07FFH 1 5 b its 0FFFH 1 5 b its H T68F14 R eset In te rru p t V e c to r
Capacity 1K14 2K15 4K15
H T68F15 R eset In te rru p t V e c to r
Program Memory Structure
Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution.
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the TABRD[m] or TABRDL[m] instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0.
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The accompanying diagram illustrates the addressing data flow of the look-up table.
Lastpage or T B H P R e g is te r T B L P R e g is te r P ro g ra m A d d re s s R e g is te r T B L H H ig h B y te M e m o ry D a ta 1 4 ~ 1 5 b its
U s e r S e le c te d R e g is te r Low B y te
Table Program Example
The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is 700H which refers to the start address of the last page within the 2K Program Memory of the HT68F14. The table pointer is setup here to have an initial value of 06H. This will ensure that the first data read from the data table will be at the Program Memory address 706H or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the TABRD [m] instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRD [m] instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation.
Table Read Program Example db ? tempreg1 tempreg2 db ? : : mov a,06h mov tblp,a mov a,07h mov tbhp,a : : tabrd tempreg1 dec tblp tabrd tempreg2 ; temporary register #1 ; temporary register #2 ; initialise low table pointer - note that this address ; is referenced ; initialise high table pointer
; transfers value in table referenced by table pointer data at ; program memory address 706H transferred to tempreg1 and TBLH ; reduce value of table pointer by one ; transfers value in table referenced by table pointer data at ; program memory address 705H transferred to tempreg2 and TBLH ; in this example the data 1AH is transferred to tempreg1 and ; data 0FH to register tempreg2 ; sets initial address of program memory
: : org 700h
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : :
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In Circuit Programming
The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows:
Holtek Writer Pin Name SDATA SCLK VPP VDD VSS Devices Pin Description Pin Name PA0 PA2 RES VDD VSS Serial Address and data -- read/write Address and data serial clock input Reset input Power Supply (5.0V) Ground
The Program Memory can be programmed serially in-circuit using this 5-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply and one line for the reset. The technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. During the programming process the RES pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the PA0 and PA2 I/O pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins.
W r ite r C o n n e c to r S ig n a ls VDD VPP SDATA SC LK VSS * * * MCU VDD RES PA0 PA2 VSS P r o g r a m m in g P in s
T o o th e r C ir c u it
Note:
* may be resistor or capacitor. The resistance of * must be greater than 1kW or the capacitance of * must be less than 1nF.
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RAM Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored.
Structure
Divided into two sections, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control.
Device HT68F13 HT68F14 HT68F15 Capacity 648 968 1928 Address 40H~7FH 40H~9FH 40H~FFH
General Purpose Data Memory Structure
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00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH H T68F13 IA R 0 MP0 IA R 1 MP1 U nused ACC PCL TBLP TBLH TBHP STATUS SMOD LVD C IN T E G W DTC TBC IN T C 0 IN T C 1 U nused U nused U nused U nused U nused U nused PAW U PAPU PA PAC PBPU PB PBC PCPU PC PCC U nused U nused U nused U nused U nused U nused U nused U nused U nused U nused U nused TM PC U nused U nused U nused U nused U nused U nused TM 1C0 TM 1C1 U nused TM 1DL TM 1DH TM 1AL TM 1AH U nused U nused SCOMC U nused U nused 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH H T68F14 IA R 0 MP0 IA R 1 MP1 U nused ACC PCL TBLP TBLH TBHP STATUS SMOD LVD C IN T E G W DTC TBC IN T C 0 IN T C 1 U nused U nused M F I0 M F I1 U nused U nused PAW U PAPU PA PAC PBPU PB PBC PCPU PC PCC PDPU PD PDC U nused U nused U nused U nused U nused U nused U nused U nused TM PC TM 0C0 TM 0C1 TM 0DL TM 0DH TM 0AL AM 0AH TM 1C0 TM 1C1 U nused TM 1DL TM 1DH TM 1AL TM 1AH U nused U nused SCOMC U nused U nused 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH H T68F15 IA R 0 MP0 IA R 1 MP1 U nused ACC PCL TBLP TBLH TBHP STATUS SMOD LVD C IN T E G W DTC TBC IN T C 0 IN T C 1 U nused U nused M F I0 M F I1 U nused U nused PAW U PAPU PA PAC PBPU PB PBC PCPU PC PCC PDPU PD PDC U nused U nused U nused U nused U nused U nused U nused U nused TM PC TM 0C0 TM 0C1 TM 0DL TM 0DH TM 0AL TM 0AH TM 1C0 TM 1C1 TM 1C2 TM 1DL TM 1DH TM 1AL TM 1AH TM 1BL TM 1BH SCOMC U nused U nused
Special Purpose Data Memory Structure
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Special Function Register Description
Most of the Special Function Register details will be described in the relevant functional section. However, several registers require a separate description in this section.
Indirect Addressing Registers - IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation.
Indirect Addressing Program Example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov mov mov mov loop: clr inc sdz jm continue: IAR0 mp0 block p loop ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared a,04h block,a a,offset adres1 mp0,a ; setup size of block ; Accumulator loaded with first RAM address ; setup memory pointer with first RAM address
The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
Memory Pointers - MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. Note that for the HT68F13 device, bit 7 of the Memory Pointers is not required to address the full memory space. When bit 7 of the Memory Pointers for HT68F13 device is read, a value of 1 will be returned. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4.
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Accumulator - ACC
The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted.
Program Counter Low Register - PCL
To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location. However, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted.
Look-up Table Registers - TBLP, TBHP, TBLH
These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the INC or DEC instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the CLR WDT or HALT instruction. The PDF flag is affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations.
*
C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
* * *
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*
PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction.
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
*
STATUS Register Bit Name R/W POR Bit 7, 6 Bit 5 7 3/4 3/4 3/4 6 3/4 3/4 3/4 5 TO R 0 4 PDF R 0 3 OV R/W x 2 Z R/W x 1 AC R/W x 0 C R/W x
x unknown
Unimplemented, read as 0 TO: Watchdog Time-Out flag 0: After power up or executing the CLR WDT or HALT instruction 1: A watchdog time-out occurred. PDF: Power down flag 0: After power up or executing the CLR WDT instruction 1: By executing the HALT instruction OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
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Oscillator
Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers.
Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator options are selected through the configuration options. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications.
Type External Crystal External RC Internal High Speed RC Internal Low Speed RC Name HXT ERC HIRC LIRC Freq. 400kHz~20MHz 8MHz 4, 8 or 12MHz 32kHz Pins OSC1/OSC2 OSC1 3/4 3/4
Oscillator Types
System Clock Configurations
There are four system oscillators, three high speed oscillators and one low speed oscillator. The high speed oscillators are the external crystal/ceramic oscillator - HXT, the external - ERC, and the internal RC oscillator - HIRC. The low speed oscillator is the internal 32 kHz oscillator - LIRC. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2~CKS0 bits in the SMOD register and as the system clock can be dynamically selected.
High Speed Oscillator HXT ERC HIRC High Speed Oscillator Configuration Option fH/32 fH/64 LIRC Low Speed Oscillator fLIRC fL HLCLK, CKS2~CKS0 bits fSUB Fast Wake-up from SLEEP Mode or IDLE Mode Control (for HXT only) fSYS fH/8 fH/16 fH 6-stage Prescaler fH/2 fH/4
System Clock Configurations
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The actual source clock used for each of the high speed and low speed oscillators is chosen via configuration options. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator.
External Crystal/ Ceramic Oscillator - HXT
The External Crystal/Ceramic System Oscillator is one of the high frequency oscillator choices, which is selected via configuration option. For most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturers specification.
C1 Rp OSC1 Rf In te r n a l O s c illa to r C ir c u it
C2
OSC2
T o in te r n a l c ir c u its
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . C 1 a n d C 2 a r e r e q u ir e d . 2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator - HXT Crystal Oscillator C1 and C2 Values Crystal Frequency 12MHz 8MHz 4MHz 1MHz Note: C1 0pF 0pF 0pF 100pF C1 and C2 values are for guidance only. Crystal Recommended Capacitor Values C2 0pF 0pF 0pF 100pF
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External RC Oscillator - ERC
Using the ERC oscillator only requires that a resistor, with a value between 24kW and 2.4MW, is connected between OSC1 and VDD, and a capacitor is connected between OSC1 and ground, providing a low cost oscillator configuration. It is only the external resistor that determines the oscillation frequency; the external capacitor has no influence over the frequency and is connected for stability purposes only. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a resistance/ frequency reference point, it can be noted that with an external 120kW resistor connected and with a 5V voltage power supply and temperature of 25C degrees, the oscillator will have a frequency of 8MHz within a tolerance of 2%. Here only the OSC1 pin is used, which is shared with I/O pin PB1, leaving pin PB2 free for use as a normal I/O pin.
V R
OSC DD
20pF
OSC1 PB2
External RC Oscillator - ERC
Internal RC Oscillator - HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has three fixed frequencies of either 4MHz, 8MHz or 12MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of either 3V or 5V and at a temperature of 25C degrees, the fixed oscillation frequency of 4MHz, 8MHz or 12MHz will have a tolerance within 2%. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins PB1 and PB2 are free for use as normal I/O pins.
Internal 32kHz Oscillator - LIRC
The Internal 32kHz System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25J degrees, the fixed oscillation frequency of 32kHz will have a tolerance within 10%.
Supplementary Oscillator
The low speed oscillator, in addition to providing a system clock source, is also used to provide a clock source to two other device functions. These are the Watchdog Timer and the Time Base Interrupts.
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Operating Modes and System Clocks
Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio.
System Clocks
The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock can come from a high frequency fH or low frequency fL source and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from either a HXT, ERC or HIRC oscillator, selected via a configuration option. The low speed system clock source can be sourced from internal clock fL. If fL is selected, then it can be sourced by the LIRC oscillator. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. Note that when the system clock source fSYS is switched to fL from fH, the high speed oscillation will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. There are two additional internal clocks for the peripheral circuits, the substitute clock, fSUB, and the Time Base clock, fTBC. These internal clocks are sourced by the LIRC oscillator. The fSUB clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. Together with fSYS/4 it is also used as one of the clock sources for the Watchdog timer. The fTBC clock is used as a source for the Time Base interrupt functions and for the TMs.
System Operation Modes
There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0, SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power.
Description Operation Mode CPU NORMAL Mode SLOW Mode IDLE0 Mode IDLE1 Mode SLEEP0 Mode SLEEP1 Mode On On On Off Off Off fSYS fH~ fH/64 fL Off On Off Off fSUB On On On On Off On fS On On On/Off On Off On fTBC On On On On Off Off
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NORMAL Mode
As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the HXT, ERC or HIRC oscillators. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current.
SLOW Mode
This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from the low speed oscillator LIRC. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off.
SLEEP0 Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fSUB and fS clocks will be stopped too, and the Watchdog Timer function is disabled. In this mode, the LVDEN is must set to 0. If the LVDEN is set to 1, it wont enter the SLEEP0 Mode.
SLEEP1 Mode
The SLEEP Mode is entered when a HALT instruction is executed and the IDLEN bit in the SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However, the fSUB and fS clocks will continue to operate if the LVDEN is set to 1 or the Watchdog Timer function is enabled and if its clock source is chosen via configuration option to come from the fSUB.
IDLE0 Mode
The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer and TMs. In the IDLE0 Mode, the system oscillator will be stopped. In the IDLE0 Mode the Watchdog Timer clock, fS, will either be on or off depending upon the fS clock source. If the source is fSYS/4, then the fS clock will be off, and if the source comes from fSUB then fS will be on.
IDLE1 Mode
The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer and TMs. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, fS, will be on. If the source is fSYS/4, then the fS clock will be on, and if the source comes from fSUB then fS will be on.
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Control Register
A single register, SMOD, is used for overall control of the internal clocks within the device.
SMOD Register Bit Name R/W POR Bit 7~5 7 CKS2 R/W 0 6 CKS1 R/W 0 5 CKS0 R/W 0 4 FSTEN R/W 0 3 LTO R 0 2 HTO R 0 1 IDLEN R/W 1 0 HLCLK R/W 1
Bit 4
Bit 3
Bit 2
Bit 1
CKS2~CKS0: The system clock selection when HLCLK is 0 000: fL (fLIRC) 001: fL (fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which is the LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. FSTEN: Fast Wake-up Control (only for HXT) 0: Disable 1: Enable This is the Fast Wake-up Control bit which determines if the fSUB clock source is initially used after the device wakes up. When the bit is high, the fSUB clock source can be used as a temporary system clock to provide a faster wake up time as the fSUB clock is available. LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after 1~2 clock cycles as the LIRC oscillator is used. HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as 1 by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if the ERC or HIRC oscillator is used. IDLEN: IDLE Mode control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational as the FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed.
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Bit 0 HLCLK: system clock selection 0: fH/2 ~ fH/64 or fL 1: fH This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fL clock is used as the system clock. When the bit is high the fH clock will be selected and if low the fH/2 ~ fH/64 or fL clock will be selected. When system clock switches from the fH clock to the fL clock, the fH clock will be automatically switched off to conserve power.
Fast Wake-up
To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system clock source to the device will be stopped. However when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is provided, which allows fSUB, namely the LIRC oscillator, to act as a temporary clock to first drive the system until the original system oscillator has stabilised. As the clock source for the Fast Wake-up function is fSUB, the Fast Wake-up function is only available in the SLEEP1 and IDLE0 modes. When the device is woken up from the SLEEP0 mode, the Fast Wake-up function has no effect because the fSUB clock is stopped. The Fast Wake-up enable/disable function is controlled using the FSTEN bit in the SMOD register. If the HXT oscillator is selected as the NORMAL Mode system clock and the Fast Wake-up function is enabled, then it will take one to two tSUB clock cycles of the LIRC oscillator for the system to wake-up. The system will then initially run under the fSUB clock source until 1024 HXT clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch over to operating from the HXT oscillator. If the ERC or HIRC oscillators or LIRC oscillator is used as the system oscillator then it will take 15~16 clock cycles of the ERC or HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases.
System Oscillator FSTEN Bit 0 HXT 1 X X X Wake-up Time (SLEEP0 Mode) 1024 HXT cycles 1024 HXT cycles 15~16 ERC cycles 15~16 HIRC cycles 1~2 LIRC cycles Wake-up Time (SLEEP1 Mode) Wake-up Time (IDLE0 Mode) Wake-up Time (IDLE1 Mode) 1~2 HXT cycles 1~2 HXT cycles 1~2 ERC cycles 1~2 HIRC cycles 1~2 LIRC cycles X : dont care Wake-Up Times Note that if the Watchdog Timer is disabled, which means that the LIRC oscillator is off, then there will be no Fast Wake-up function available when the device wakes-up from the SLEEP0 Mode.
1024 HXT cycles 1~2 fSUB cycles (System runs with fSUB first for 1024 HXT cycles and then switches over to run with the HXT clock) 15~16 ERC cycles 15~16 HIRC cycles 1~2 LIRC cycles
ERC HIRC LIRC
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fS
NORMAL Y S = fH ~ fH /6 4 fH o n C P U ru n fS Y S o n fT B C o n fS U B o n
ID L E 1 H A L T in s tr u c tio n is e x e c u te d C P U s to p ID L E N = 1 FSYSO N=1 fS Y S o n fT B C o n fS U B o n
SLEEP0 H A L T in s tr u c tio n is e x e c u te d fS Y S o ff C P U s to p ID L E N = 0 fT B C o ff fS U B o ff W D T & L V D o ff SLEEP1 H A L T in s tr u c tio n is e x e c u te d fS Y S o ff C P U s to p ID L E N = 0 fT B C o ff fS U B o n W D T orLVD on SLOW fS Y S = fL fL o n C P U ru n fS Y S o n fT B C o n fS U B o n fH o ff
ID L E 0 H A L T in s tr u c tio n is e x e c u te d C P U s to p ID L E N = 1 FSYSO N=0 fS Y S o ff fT B C o n fS U B o n
Operating Mode Switching
The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the WDTC register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs. The accompanying flowchart shows what happens when the device moves between the various operating modes.
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NORMAL Mode to SLOW Mode Switching
When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to 0 and set the CKS2~CKS0 bits to 000B or 001B in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC oscillator and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register.
NO RM AL M ode C K S 2 ~ C K S 0 = 00xB & HLCLK = 0 SLO W M ode
W D T a n d L V D a r e a ll o ff ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d SLEEP0 M ode W D T o r L V D is o n ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d SLEEP1 M ode
ID L E N = 1 , F S Y S O N = 0 H A L T in s tr u c tio n is e x e c u te d
ID E L 0 M o d e ID L E N = 1 , F S Y S O N = 1 H A L T in s tr u c tio n is e x e c u te d ID L E 1 M o d e
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SLOW Mode to NORMAL Mode Switching
In SLOW Mode the system uses the LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to 1 or HLCLK bit is 0 but CKS2~CKS0 is set to 010B, 011B, 100B, 101B, 110B or 111B. As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used.
NO RM AL M ode C K S 2 ~ C K S 0 = 00xB & HLCLK = 0 SLO W M ode
W D T a n d L V D a r e a ll o ff ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d SLEEP0 M ode W D T o r L V D is o n ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d SLEEP1 M ode
ID L E N = 1 , F S Y S O N = 0 H A L T in s tr u c tio n is e x e c u te d
ID E L 0 M o d e ID L E N = 1 , F S Y S O N = 1 H A L T in s tr u c tio n is e x e c u te d ID L E 1 M o d e
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Entering the SLEEP0 Mode
There is only one way for the device to enter the SLEEP0 Mode and that is to execute the HALT instruction in the application program with the IDLEN bit in SMOD register equal to 0 and the WDT and LVD both off. When this instruction is executed under the conditions described above, the following will occur:
*
The system clock, WDT clock and Time Base clock will be stopped and the application program will stop at the HALT instruction. The Data Memory contents and registers will maintain their present condition. The WDT will be cleared and stopped no matter if the WDT clock source originates from the fSUB clock or from the system clock. The I/O ports will maintain their present conditions. In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared.
* * * *
Entering the SLEEP1 Mode
There is only one way for the device to enter the SLEEP1 Mode and that is to execute the HALT instruction in the application program with the IDLEN bit in SMOD register equal to 0 and the WDT or LVD on. When this instruction is executed under the conditions described above, the following will occur:
*
The system clock and Time Base clock will be stopped and the application program will stop at the HALT instruction, but the WDT or LVD will remain with the clock source coming from the fSUB clock. The Data Memory contents and registers will maintain their present condition. The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock as the WDT is enabled. The I/O ports will maintain their present conditions. In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared.
* * * *
Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the HALT instruction in the application program with the IDLEN bit in SMOD register equal to 1 and the FSYSON bit in WDTC register equal to 0. When this instruction is executed under the conditions described above, the following will occur:
* * *
The system clock will be stopped and the application program will stop at the HALT instruction, but the Time Base clock and fSUB clock will be on. The Data Memory contents and registers will maintain their present condition. The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock and the WDT is enabled. The WDT will stop if its clock source originates from the system clock. The I/O ports will maintain their present conditions. In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared.
* *
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Entering the IDLE1 Mode
There is only one way for the device to enter the IDLE1 Mode and that is to execute the HALT instruction in the application program with the IDLEN bit in SMOD register equal to 1 and the FSYSON bit in the WDTC register equal to 1. When this instruction is executed under the conditions described above, the following will occur:
*
The system clock, Time Base clock and fSUB clock will be on and the application program will stop at the HALT instruction. The Data Memory contents and registers will maintain their present condition. The WDT will be cleared and resume counting if the WDT is enabled regardless of the WDT clock source which originates from the fSUB clock or from the system clock. The I/O ports will maintain their present conditions. In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared.
* * * *
Standby Current Considerations
As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LIRC oscillator have been enabled. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps.
Wake-up
After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows:
* * * *
An external reset An external falling edge on Port A A system interrupt A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status.
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Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the HALT instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the HALT instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled.
Programming Considerations
If the device is woken up from the SLEEP1 Mode to NORMAL Mode, and the system clock source is from the HXT oscillator and FSTEN is 1, the system clock can first be switched to the LIRC oscillator after wake up. There are peripheral functions, such as WDT and TMs, for which the fSYS is used. If the system clock source is switched from fH to fL, the clock source to the peripheral functions mentioned above will change accordingly. The on/off condition of fSUB and fS depends upon whether the WDT is enabled or disabled as the WDT clock source is selected from fSUB.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by one of two sources selected by configuration option: fSUB or fSYS/4. The fSUB clock is sourced from the LIRC oscillator. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The other Watchdog Timer clock source option is the fSYS/4 clock. The Watchdog Timer clock source can originate from the fSUB clock, i.e. its own internal LIRC oscillator or fSYS/4 determined by a configuration option. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 215 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register.
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Watchdog Timer Control Register
A single register, WDTC, controls the required timeout period as well as the enable/disable operation. This register together with several configuration options control the overall operation of the Watchdog Timer.
WDTC Register Bit Name R/W POR Bit 7 7 FSYSON R/W 0 6 WS2 R/W 1 5 WS1 R/W 1 4 WS0 R/W 1 3 WDTEN3 R/W 1 2 WDTEN2 R/W 0 1 WDTEN1 R/W 1 0 WDTEN0 R/W 0
Bit 6 ~ 4
Bit 3 ~ 0
FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable WS2, WS1, WS0 : WDT time-out period selection 000: 256/fS 001: 512/fS 010: 1024/fS 011: 2048/fS 100: 4096/fS 101: 8192/fS 110: 16384/fS 111: 32768/fS WDTEN3, WDTEN2, WDTEN1, WDTEN0 : WDT Software Control 1010: Disable Other: Enable
Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. Some of the Watchdog Timer options, such as enable/disable, clock source selection and clear instruction type are selected using configuration options. In addition to a configuration option to enable/disable the Watchdog Timer, there are also four bits, WDTEN3~WDTEN0, in the WDTC register to offer an additional enable/disable control of the Watchdog Timer. To disable the Watchdog Timer, as well as the configuration option being set to disable, the WDTEN3 ~ WDTEN0 bits must also be set to a specific value of 1010B. Any other values for these bits will keep the Watchdog Timer enabled, irrespective of the configuration enable/disable setting. After power on these bits will have the value of 1010. If the Watchdog Timer is used, it is recommended that they are set to a value of 0101B for maximum noise immunity. Note that if the Watchdog Timer has been disabled, then any instruction relating to its operation will result in no operation.
WDT Configuration Option WDT Enable WDT Disable WDT Disable WDTEN3~WDTEN0 Bits xxxx Except 1010 1010 WDT Enable Enable Disable
x: dont care.
Watchdog Timer Enable/Disable Control
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Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an external hardware reset, which means a low level on the RES pin, the second is using the Watchdog Timer software clear instructions and the third is via a HALT instruction. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single CLR WDT instruction while the second is to use the two commands CLR WDT1 and CLR WDT2. For the first option, a simple execution of CLR WDT will clear the WDT while for the second option, both CLR WDT1 and CLR WDT2 must both be executed alternately to successfully clear the Watchdog Timer. Note that for this second option, if CLR WDT1 is used to clear the Watchdog Timer, successive executions of this instruction will have no effect, only the execution of a CLR WDT2 instruction will clear the Watchdog Timer. Similarly after the CLR WDT2 instruction has been executed, only a successive CLR WDT1 instruction can clear the Watchdog Timer. The maximum time out period is when the 215division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 215 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. If the fSYS/4 clock is used as the Watchdog Timer clock source, it should be noted that when the system enters the SLEEP or IDLE0 Mode, then the instruction clock is stopped and the Watchdog Timer may lose its protecting purposes. For systems that operate in noisy environments, using the fSUB clock source is strongly recommended.
CLR CLR W D T 1 F la g W D T 2 F la g C le a r W D T T y p e C o n fig u r a tio n O p tio n fS /2
8
1 o r 2 In s tr u c tio n s
fS
YS
/4
M
UB
fS
U X
fS
CLR W D T P r e s c a le r 8 -to -1 M U X W S2~W S0 (fS /2 8 ~ fS /2 15) W D T T im e - o u t (2 8 /fS ~ 2 15/fS )
8 - s ta g e D iv id e r
C o n fig u r a tio n O p tio n
Watchdog Timer
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Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to precede with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold.
Reset Functions
There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally:
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs.
VDD RES In te rn a l R e s e t 0 .9 V
DD
t RR
SS TT DD ++
t SS
SS TT
Note: tRSTD is power-on delay, typical time=100ms Power-On Reset Timing Chart
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RES Pin Reset
As the reset pin is shared with PB.3, the reset function must be selected using a configuration option. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference. For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended.
0 .0 1 m F * * 1N4148* V
DD
VDD 10kW ~ 100kW 300W * P B 3 /R E S
0 .1 ~ 1 m F
VSS
Note:
* It is recommended that this component is added for added ESD protection ** It is recommended that this component is added in environments where power line noise is significant External RES Circuit
More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website. Pulling the RES Pin low using external hardware will also execute a device reset. In this case, as in the case of other resets, the Program Counter will reset to zero and program execution initiated from this point.
RES In te rn a l R e s e t 0 .4 V
DD
0 .9 V
DD
tR
STD
+
tS
ST
Note: tRSTD is power-on delay, typical time=100ms RES Reset Timing Chart
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Low Voltage Reset - LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected via configuration options.
LVR In te rn a l R e s e t
tR
STD
+
tS
ST
Note: tRSTD is power-on delay, typical time=100ms Low Voltage Reset Timing Chart Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to 1.
W D T T im e - o u t
tR
In te rn a l R e s e t
STD
+
tS
ST
Note: tRSTD is power-on delay, typical time=100ms WDT Time-out Reset during Normal Operation Timing Chart
Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1. Refer to the A.C. Characteristics for tSST details.
W D T T im e - o u t In te rn a l R e s e t
tS
ST
Note:
The tSST is 15~16 clock cycles if the system clock source is provided by ERC or HIRC. The tSST is 1024 clock for HXT. The tSST is 1~2 clock for LIRC. WDT Time-out Reset during SLEEP or IDLE Timing Chart
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Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table:
TO 0 u 1 1 PDF 0 u u 1 Power-on reset RES or LVR reset during NORMAL or SLOW Mode operation WDT time-out reset during NORMAL or SLOW Mode operation WDT time-out reset during IDLE or SLEEP Mode operation RESET Conditions
Note: u stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs.
Item Program Counter Interrupts WDT Timer/Event Counter Input/Output Ports Stack Pointer Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting Timer Counter will be turned off I/O ports will be setup as inputs Stack Pointer will point to the top of the stack Condition After RESET
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers.
HT68F13 Register Register MP0 MP1 ACC PCL TBLP TBHP TBLH STATUS SMOD LVDC INTEG WDTC TBC Reset (Power-on) 1xxx xxxx 1xxx xxxx xxxx xxxx 0000 0000 xxxx xxxx ---- --xx --xx xxxx --00 xxxx 0000 0011 --00 -000 ---- 0000 0111 1010 0011 ---RES or LVR Reset 1xxx xxxx 1xxx xxxx uuuu uuuu 0000 0000 uuuu uuuu ---- --uu --uu uuuu --uu uuuu 0000 0011 --00 -000 ---- 0000 0111 1010 0011 ---WDT Time-out (Normal Operation) 1xxx xxxx 1xxx xxxx uuuu uuuu 0000 0000 uuuu uuuu ---- --uu --uu uuuu --1u uuuu 0000 0011 --00 -000 ---- 0000 0111 1010 0011 ---WDT Time-out (IDLE) 1uuu uuuu 1uuu uuuu uuuu uuuu 0000 0000 uuuu uuuu ---- --uu --uu uuuu --11 uuuu uuuu uuuu --uu -uuu ---- uuuu uuuu uuuu uuuu ----
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Register INTC0 INTC1 PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC TMPC TM1C0 TM1C1 TM1DL TM1DH TM1AL TM1AH SCOMC Note: Reset (Power-on) -000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---- --00 ---- --11 ---- --11 --01 ---0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 RES or LVR Reset -000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---- --00 ---- --11 ---- --11 --01 ---0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 WDT Time-out (Normal Operation) -000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---- --00 ---- --11 ---- --11 --01 ---0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 WDT Time-out (IDLE) -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu ---- --uu ---- --uu --uu ---uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu
u stands for unchanged x stands for unknown - stands for unimplemented
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
HT68F14 Register Register MP0 MP1 ACC PCL TBLP TBLH TBHP STATUS SMOD LVDC INTEG WDTC TBC INTC0 INTC1 MFI0 MFI1 PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC PDPU PD PDC TMPC TM0C0 TM0C1 TM0DL TM0DH TM0AL Reset (Power-on) xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx -xxx xxxx ---- -xxx --00 xxxx 0000 0011 --00 -000 ---- 0000 0111 1010 0011 ----000 0000 0000 0000 --00 --00 --00 --00 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---- 0000 ---- 1111 ---- 1111 ---- --00 ---- --11 ---- --11 --01 --01 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 RES or LVR Reset xxxx xxxx xxxx xxxx uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---- -uuu --uu uuuu 0000 0011 --00 -000 ---- 0000 0111 1010 0011 ----000 0000 0000 0000 --00 --00 --00 --00 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---- 0000 ---- 1111 ---- 1111 ---- --00 ---- --11 ---- --11 --01 --01 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---- -uuu --1u uuuu 0000 0011 --00 -000 ---- 0000 0111 1010 0011 ----000 0000 0000 0000 --00 --00 --00 --00 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---- 0000 ---- 1111 ---- 1111 ---- --00 ---- --11 ---- --11 --01 --01 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 WDT Time-out (IDLE) uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---- -uuu --11 uuuu uuuu uuuu --uu -uuu ---- uuuu uuuu uuuu uuuu ----uuu uuuu uuuu uuuu --uu --uu --uu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu ---- uuuu ---- --uu ---- --uu ---- --uu --uu --uu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Register TM0AH TM1C0 TM1C1 TM1DL TM1DH TM1AL TM1AH SCOMC Note: Reset (Power-on) ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 RES or LVR Reset ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 WDT Time-out (Normal Operation) ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 WDT Time-out (IDLE) ---- --uu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu
u stands for unchanged x stands for unknown - stands for unimplemented
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HT68F15 Register Register MP0 MP1 ACC PCL TBLP TBLH TBHP STATUS SMOD LVDC INTEG WDTC TBC INTC0 INTC1 MFI0 MFI1 PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC PDPU PD PDC TMPC TM0C0 TM0C1 TM0DL TM0DH TM0AL Reset (Power-on) xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx -xxx xxxx ---- xxxx --00 xxxx 0000 0011 --00 -000 ---- 0000 0111 1010 0011 ----000 0000 0000 0000 --00 --00 -000 -000 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---- --00 ---- --11 ---- --11 1001 --01 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 RES or LVR Reset xxxx xxxx xxxx xxxx uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---- uuuu --uu uuuu 0000 0011 --00 -000 ---- 0000 0111 1010 0011 ----000 0000 0000 0000 --00 --00 -000 -000 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---- --00 ---- --11 ---- --11 1001 --01 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---- uuuu --1u uuuu 0000 0011 --00 -000 ---- 0000 0111 1010 0011 ----000 0000 0000 0000 --00 --00 -000 -000 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---- --00 ---- --11 ---- --11 1001 --01 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 WDT Time-out (IDLE) uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---- uuuu --11 uuuu uuuu uuuu --uu -uuu ---- uuuu uuuu uuuu uuuu ----uuu uuuu uuuu uuuu --uu --uu -uuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu ---- --uu ---- --uu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu
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Register TM0AH TM1C0 TM1C1 TM1C2 TM1DL TM1DH TM1AL TM1AH TM1BL TM1BH SCOMC Note: Reset (Power-on) ---- --00 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 RES or LVR Reset ---- --00 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 WDT Time-out (Normal Operation) ---- --00 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 WDT Time-out (IDLE) ---- --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu
u stands for unchanged x stands for unknown - stands for unimplemented
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PD. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction MOV A,[m], where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten.
I/O Register List
HT68F13 Register Name PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC HT68F14 Register Name PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC PDPU PD PDC Bit 7 D7 D7 D7 D7 D7 D7 D7 3/4 3/4 3/4 3/4 3/4 3/4 6 D6 D6 D6 D6 D6 D6 D6 3/4 3/4 3/4 3/4 3/4 3/4 5 D5 D5 D5 D5 D5 D5 D5 3/4 3/4 3/4 3/4 3/4 3/4 4 D4 D4 D4 D4 D4 D4 D4 3/4 3/4 3/4 3/4 3/4 3/4 3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 3/4 3/4 3/4 2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 3/4 3/4 3/4 1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 Bit 7 D7 D7 D7 D7 D7 D7 D7 3/4 3/4 3/4 6 D6 D6 D6 D6 D6 D6 D6 3/4 3/4 3/4 5 D5 D5 D5 D5 D5 D5 D5 3/4 3/4 3/4 4 D4 D4 D4 D4 D4 D4 D4 3/4 3/4 3/4 3 D3 D3 D3 D3 D3 D3 D3 3/4 3/4 3/4 2 D2 D2 D2 D2 D2 D2 D2 3/4 3/4 3/4 1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0
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HT68F15 Register Name PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC PDPU PD PDC Bit 7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 3/4 3/4 3/4 6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 3/4 3/4 3/4 5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 3/4 3/4 3/4 4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 3/4 3/4 3/4 3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 3/4 3/4 3/4 2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 3/4 3/4 3/4 1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
C o n tr o l B it D Q CK S Q
P u ll- H ig h R e g is te r S e le c t
V
DD
W eak P u ll- u p
D a ta B it Q D CK S Q M U X
I/O
p in
W r ite D a ta R e g is te r
R e a d D a ta R e g is te r S y s te m W a k e -u p
W a k e - u p S e le c t
P A o n ly
Generic Input/Output Structure
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PDPU and are implemented using weak PMOS transistors.
PAPU Register Bit Name R/W POR Bit 7~0 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0
I/O Port A bit 7 ~ bit 0 pull-high control 0: disable 1: enable PBPU Register
Bit Name R/W POR Bit 7~0
7 D7 R/W 0
6 D6 R/W 0
5 D5 R/W 0
4 D4 R/W 0
3 D3 R/W 0
2 D2 R/W 0
1 D1 R/W 0
0 D0 R/W 0
I/O Port B bit 7 ~ bit 0 pull-high control 0: disable 1: enable PCPU Register - HT68F13
Bit Name R/W POR Bit 7~2 Bit 1~0
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 3/4 3/4 3/4
3 3/4 3/4 3/4
2 3/4 3/4 3/4
1 D1 R/W 0
0 D0 R/W 0
3/4 Unimplemented, read as 0 I/O Port C bit 1 ~ bit 0 pull-high control 0: disable 1: enable PCPU Register - HT68F14
Bit Name R/W POR Bit 7~4 Bit 3~0
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 3/4 3/4 3/4
3 D3 R/W 0
2 D2 R/W 0
1 D1 R/W 0
0 D0 R/W 0
3/4 Unimplemented, read as 0 I/O Port C bit 3 ~ bit 0 pull-high control 0: disable 1: enable
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
PCPU Register - HT68F15 Bit Name R/W POR Bit 7~0 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0
I/O Port C bit 7 ~ bit 0 pull-high control 0: disable 1: enable PDPU Register - HT68F14, HT68F15
Bit Name R/W POR Bit 7~2 Bit 1~0
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 3/4 3/4 3/4
3 3/4 3/4 3/4
2 3/4 3/4 3/4
1 D1 R/W 0
0 D0 R/W 0
3/4 Unimplemented, read as 0 I/O Port D bit 1 ~ bit 0 pull-high control 0: disable 1: enable
Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register.
PAWU Register Bit Name R/W POR Bit 7~0 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0
PAWU: Port A bit 7 ~ bit 0 wake-up control 0: disable 1: enable
I/O Port Control Registers
Each I/O port has its own control register known as PAC~PDC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as 1. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as 0, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin.
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
PAC Register Bit Name R/W POR Bit 7~0 7 D7 R/W 1 6 D6 R/W 1 5 D5 R/W 1 4 D4 R/W 1 3 D3 R/W 1 2 D2 R/W 1 1 D1 R/W 1 0 D0 R/W 1
I/O Port A bit 7 ~ bit 0 input/output control 0: output 1: input PBC Register
Bit Name R/W POR Bit 7~0
7 D7 R/W 1
6 D6 R/W 1
5 D5 R/W 1
4 D4 R/W 1
3 D3 R/W 1
2 D2 R/W 1
1 D1 R/W 1
0 D0 R/W 1
I/O Port B bit 7 ~ bit 0 input/output control 0: output 1: input PCC Register - HT68F13
Bit Name R/W POR Bit 7~2 Bit 1~0
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 3/4 3/4 3/4
3 3/4 3/4 3/4
2 3/4 3/4 3/4
1 D1 R/W 1
0 D0 R/W 1
3/4 Unimplemented, read as 0 I/O Port C bit 1 ~ bit 0 input/output control 0: output 1: input PCC Register - HT68F14
Bit Name R/W POR Bit 7~4 Bit 3~0
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 3/4 3/4 3/4
3 D3 R/W 1
2 D2 R/W 1
1 D1 R/W 1
0 D0 R/W 1
3/4 Unimplemented, read as 0 I/O Port C bit 3 ~ bit 0 input/output control 0: output 1: input PCC Register - HT68F15
Bit Name R/W POR Bit 7~0
7 D7 R/W 1
6 D6 R/W 1
5 D5 R/W 1
4 D4 R/W 1
3 D3 R/W 1
2 D2 R/W 1
1 D1 R/W 1
0 D0 R/W 1
I/O Port C bit 7 ~ bit 0 input/output control 0: output 1: input
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
PDC Register - HT68F14, HT68F15 Bit Name R/W POR Bit 7~2 Bit 1~0 7 3/4 3/4 3/4 6 3/4 3/4 3/4 5 3/4 3/4 3/4 4 3/4 3/4 3/4 3 3/4 3/4 3/4 2 3/4 3/4 3/4 1 D1 R/W 0 0 D0 R/W 0
3/4 Unimplemented, read as 0 I/O Port D bit 1 ~ bit 0 input/output control 0: output 1: input
I/O Pin Structures
The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. The diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins.
Programming Considerations
Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PDC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PD, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the SET [m].i and CLR [m].i instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Timer Modules - TM
One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has either two or three individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact, Standard and Enhanced TM sections.
Introduction
The devices contain up to two TMs with each TM having a reference name of TM0 and TM1. Each individual TM can be categorised as a certain type, namely Compact Type TM (CTM), Standard Type TM (STM) or Enhanced Type TM (ETM). Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact, Standard and Enhanced TMs will be described in this section and the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the three types of TMs are summarised in the accompanying table.
Function Timer/Counter I/P Capture Compare Match Output PWM Channels Single Pulse Output PWM Alignment PWM Adjustment Period & Duty CTM O 3/4 O 1 3/4 Edge Duty or Period TM Function Summary STM O O O 1 1 Edge Duty or Period ETM O O O 2 2 Edge & Centre Duty or Period
Each device in the series contains a specific number of either Compact Type, Standard Type and Enhanced Type TM units which are shown in the table together with their individual reference name, TM0~TM1.
Device HT68F13 HT68F14 HT68F15 TM0 3/4 10-bit CTM 10-bit CTM TM1 10-bit STM 10-bit STM 10-bit ETM
TM Name/Type Reference
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TM Operation
The three different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin.
TM Clock Source
The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM control registers. The clock source can be a ratio of either the system clock fSYS or the high speed clock fH, the fTBC clock source or the external TCKn pin. Note that setting these bits to the value 101 will select a reserved clock input, in effect disconnecting the TM clock source. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting.
TM Interrupts
The Compact and Standard type TMs each have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. As the Enhanced type TM has three internal comparators and comparator A or comparator B or comparator P compare match functions, it consequently has three internal interrupts. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin.
TM External Pins
Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TMs each have one or more output pins with the label TPn. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using registers. A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of output pins for each TM type and device is different, the details are provided in the accompanying table.
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All TM output pin names have an _n suffix. Pin names that include a _1 or _2 suffix indicate that they are from a TM with multiple output pins. This allows the TM to generate a complimentary output pair, selected using the I/O register data bits.
Device HT68F13 HT68F14 HT68F15 CTM 3/4 TP0_0, TP0_1 TP0_0, TP0_1 STM TP1_0, TP1_1 TP1_0, TP1_1 3/4 TM Output Pins ETM 3/4 3/4 TP1A, TP1B_0, TP1B_1, TP1B_2 Registers TMPC TMPC TMPC
TM Input/Output Pin Control Registers
Selecting to have a TM input/output or whether to retain its other shared function is implemented using one register, with a single bit in each register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function.
TMPC Register Bit Device 7 HT68F13 HT68F14 HT68F15 3/4 3/4 T1ACP0 6 3/4 3/4 T1BCP2 5 T1CP1 T1CP1 T1BCP1 4 T1CP0 T1CP0 T1BCP0 3 3/4 3/4 3/4 2 3/4 3/4 3/4 1 3/4 T0CP1 T0CP1 0 3/4 T0CP0 T0CP0
TM Input/Output Pin Control Registers List
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
P A 7 O u tp u t F u n c tio n 0 1 0 1 PA7 P B 6 O u tp u t F u n c tio n 0 1 0 1 PB6 1 0 T1C P1 1 0 T1C P0 P A 6 /T C K 1 C a p tu re In p u t TM 1 (S T M ) T1C P1 O u tp u t P B 6 /T P 1 _ 1 T1C P0
P A 7 /T P 1 _ 0
T C K In p u t
HT68F13 TM Function Pin Control Block Diagram Note: 1. The I/O register data bits shown are used for TM output inversion control. 2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input.
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P A 5 O u tp u t F u n c tio n 0 1 PA5 P C 1 O u tp u t F u n c tio n O u tp u t 0 1 PC1 P A 4 /T C K 0 P A 7 O u tp u t F u n c tio n 0 1 0 1 PA7 P B 6 O u tp u t F u n c tio n 0 1 0 1 PB6 1 0 T1C P1 1 0 T1C P0 T C K In p u t P A 6 /T C K 1 C a p tu re In p u t TM 1 (S T M ) T1C P1 O u tp u t P B 6 /T P 1 _ 1 T1C P0 TM 0 (C T M ) T C K In p u t 1 T0C P1 0 P C 1 /T P 0 _ 1 1 T0C P0 0 P A 5 /T P 0 _ 0
P A 7 /T P 1 _ 0
HT68F14 TM0 & TM1 Function Pin Control Block Diagram Note: 1. The I/O register data bits shown are used for TM output inversion control. 2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input.
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P A 5 O u tp u t F u n c tio n 0 1 PA5 P C 1 O u tp u t F u n c tio n O u tp u t 0 1 PC1 P A 4 /T C K 0 TM 0 (C T M ) T C K In p u t 1 T0C P1 0 P C 1 /T P 0 _ 1 1 T0C P0 0 P A 5 /T P 0 _ 0
P C 0 O u tp u t F u n c tio n C C R A O u tp u t 1
0
P C 0 /T P 1 A
T1AC P0 C C R A C a p tu re In p u t 0 T1AC P0 1
P A 7 O u tp u t F u n c tio n 0 1 0 1 PA7 P B 6 O u tp u t F u n c tio n 0 1 0 1 TM 1 (E T M ) PB6 P B 7 O u tp u t F u n c tio n 0 1 0 1 PB7 1 0 C C R B C a p tu re In p u t C C R B O u tp u t
P A 7 /T P 1 B _ 0
T1BC P0
P B 6 /T P 1 B _ 1
T1BC P1
P B 7 /T P 1 B _ 2
T1BC P2
T1BC P2 1 0 T1BC P1 1 0 T1BC P0 P A 6 /T C K 1
T C K In p u t
HT68F15 TM0 & TM1 Function Pin Control Block Diagram Note: 1. The I/O register data bits shown are used for TM output inversion control. 2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input.
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
TMPC Register - HT68F13 Bit Name R/W POR Bit 7, 6 Bit 5 7 3/4 3/4 3/4 6 3/4 3/4 3/4 5 T1CP1 R/W 0 4 T1CP0 R/W 1 3 3/4 3/4 3/4 2 3/4 3/4 3/4 1 3/4 3/4 3/4 0 3/4 3/4 3/4
Unimplemented, read as 0 T1CP1: TP1_1 pin enable control 0: disable 1: enable T1CP0: TP1_0 pin enable control 0: disable 1: enable Unimplemented, read as 0 TMPC Register - HT68F14
Bit 4
Bit 3~0
Bit Name R/W POR Bit 7~6 Bit 5
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 T1CP1 R/W 0
4 T1CP0 R/W 1
3 3/4 3/4 3/4
2 3/4 3/4 3/4
1 T0CP1 R/W 0
0 T0CP0 R/W 1
Bit 4
Unimplemented, read as 0 T1CP1: TP1_1 pin enable control 0: disable 1: enable T1CP0: TP1_0 pin enable control 0: disable 1: enable Unimplemented, read as 0 T0CP1: TP0_1 pin enable control 0: disable 1: enable T0CP0: TP0_0 pin enable control 0: disable 1: enable
Bit 3~2 Bit 1
Bit 0
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
TMPC Register - HT68F15 Bit Name R/W POR Bit 7 7 T1ACP0 R/W 1 6 T1BCP2 R/W 0 5 T1BCP1 R/W 0 4 T1BCP0 R/W 1 3 3/4 3/4 3/4 2 3/4 3/4 3/4 1 T0CP1 R/W 0 0 T0CP0 R/W 1
Bit 6
Bit 5
T1ACP0: TP1A pin enable control 0: disable 1: enable T1BCP2: TP1B_2 pin enable control 0: disable 1: enable T1BCP1: TP1B_1 pin enable control 0: disable 1: enable T1BCP0: TP1B_0 pin enable control 0: disable 1: enable Unimplemented, read as 0 T0CP1: TP0_1 pin enable control 0: disable 1: enable T0CP0: TP0_0 pin enable control 0: disable 1: enable
Bit 4
Bit 3~2 Bit 1
Bit 0
Programming Considerations
The TM Counter Registers and the Capture/Compare CCRA and CCRB registers, being either 10-bit or 16-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed.
TM Counter Register (Read only)
TMxDL 8-bit Buffer
TMxDH
TMxAL
TMxAH
TM CCRA Register (Read/Write)
TMxBL
TMxBH
Data Bus
TM CCRB Register (Read/Write)
As the CCRA and CCRB registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to use the MOV instruction to access the CCRA and CCRB low byte registers, named TMxAL and TMxBL, using the following access procedures. Accessing the CCRA or CCRB low byte registers without following these access procedures will result in unpredictable values.
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
The following steps show the read and write procedures:
*
Writing Data to CCRB or CCRA
Step 1. Write data to Low Byte TMxAL or TMxBL - note that here data is only written to the 8-bit
buffer.
Step 2. Write data to High Byte TMxAH or TMxBH - here data is written directly to the high byte
registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers.
*
Reading Data from the Counter Registers and CCRB or CCRA
Step
1. Read data from the High Byte TMxDH, TMxAH or TMxBH - here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. 8-bit buffer.
Step 2. Read data from the Low Byte TMxDL, TMxAL or TMxBL - this step reads data from the
Compact Type TM - CTM
Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive one or two external output pins. These two external output pins can be the same signal or the inverse signal.
CTM HT68F13 HT68F14, HT68F15 Name 3/4 10-bit CTM TM No. 3/4 0 TM Input Pin 3/4 TCK0 TM Output Pin 3/4 TP0_0, TP0_1
Compact TM Operation
At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits.
CCRP
3 - b it C o m p a r a to r P
C o m p a ra to r P M a tc h
T n P F In te rru p t
fS
YS
/4
YS
fS
fH /1 6 fH /6 4 fT B C R e s e rv e d TCKn
000 001 010 011 100 101 110 111 TnO N TnPAU
b7~b9
TnO C TPn_0 TPn_1
1 0 - b it C o u n t- u p C o u n te r
C o u n te r C le a r 0 1
O u tp u t C o n tro l
P o la r ity C o n tro l
T P n P in O u tp u t
b0~b9
TnC CLR
TnM 1,TnM 0 T n IO 1 , T n IO 0
TnPO L
1 0 - b it C o m p a r a to r A TnC K2~TnC K0 CCRA
C o m p a ra to r A
M a tc h
T n A F In te rru p t
Compact Type TM Block Diagram
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers.
Compact Type TM Register Description
Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits.
CTM Register List - HT68F14/HT68F15 Name TM0C0 TM0C1 TM0DL TM0DH TM0AL TM0AH Bit7 T0PAU T0M1 D7 3/4 D7 3/4 Bit6 T0CK2 T0M0 D6 3/4 D6 3/4 Bit5 T0CK1 T0IO1 D5 3/4 D5 3/4 Bit4 T0CK0 T0IO0 D4 3/4 D4 3/4 Bit3 T0ON T0OC D3 3/4 D3 3/4 Bit2 T0RP2 T0POL D2 3/4 D2 3/4 Bit1 T0RP1 T0DPX D1 D9 D1 D9 Bit0 T0RP0 T0CCLR D0 D8 D0 D8
10-bit Compact TM Register List TM0DL Register Bit Name R/W POR Bit 7~0 7 D7 R 0 6 D6 R 0 5 D5 R 0 4 D4 R 0 3 D3 R 0 2 D2 R 0 1 D1 R 0 0 D0 R 0
TM0DL: TM0 Counter Low Byte Register bit 7 ~ bit 0 TM0 10-bit Counter bit 7 ~ bit 0 TM0DH Register
Bit Name R/W POR Bit 7~2 Bit 1~0
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 3/4 3/4 3/4
3 3/4 3/4 3/4
2 3/4 3/4 3/4
1 D9 R 0
0 D8 R 0
Unimplemented, read as 0 TM0DH: TM0 Counter High Byte Register bit 1 ~ bit 0 TM0 10-bit Counter bit 9 ~ bit 8
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
TM0AL Register Bit Name R/W POR Bit 7~0 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0
TM0AL: TM0 CCRA Low Byte Register bit 7 ~ bit 0 TM0 10-bit CCRA bit 7 ~ bit 0 TM0AH Register
Bit Name R/W POR Bit 7~2 Bit 1~0
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 3/4 3/4 3/4
3 3/4 3/4 3/4
2 3/4 3/4 3/4
1 D9 R/W 0
0 D8 R/W 0
Unimplemented, read as 0 TM0AH: TM0 CCRA High Byte Register bit 1 ~ bit 0 TM0 10-bit CCRA bit 9 ~ bit 8 TM0C0 Register
Bit Name R/W POR Bit 7
7 T0PAU R/W 0
6 T0CK2 R/W 0
5 T0CK1 R/W 0
4 T0CK0 R/W 0
3 T0ON R/W 0
2 T0RP2 R/W 0
1 T0RP1 R/W 0
0 T0RP0 R/W 0
Bit 6~4
Bit 3
T0PAU: TM0 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. T0CK2~T0CK0: Select TM0 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: undefined 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. T0ON: TM0 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T0OC bit, when the T0ON bit changes from low to high.
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Bit 2~0 T0RP2~T0RP0: TM0 CCRP 3-bit register, compared with the TM0 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM0 clocks 001: 128 TM0 clocks 010: 256 TM0 clocks 011: 384 TM0 clocks 100: 512 TM0 clocks 101: 640 TM0 clocks 110: 768 TM0 clocks 111: 896 TM0 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter's highest three bits. The result of this comparison can be selected to clear the internal counter if the T0CCLR bit is set to zero. Setting the T0CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. TM0C1 Register Bit Name R/W POR Bit 7~6 7 T0M1 R/W 0 6 T0M0 R/W 0 5 T0IO1 R/W 0 4 T0IO0 R/W 0 3 T0OC R/W 0 2 T0POL R/W 0 1 T0DPX R/W 0 0 T0CCLR R/W 0
Bit 5~4
T0M1~T0M0: Select TM0 Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T0M1 and T0M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. T0IO1~T0IO0: Select TP0_0, TP0_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Undefined Timer/counter Mode unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T0IO1 and T0IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T0OC bit in the TM0C1 register. Note that the output level requested by the T0IO1 and T0IO0 bits must be different from the initial value setup using the T0OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T0ON bit from low to high.
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
In the PWM Mode, the T0IO1 and T0IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the T0IO1 and T0IO0 bits only after the TMn has been switched off. Unpredictable PWM outputs will occur if the T0IO1 and T0IO0 bits are changed when the TM is running T0OC: TP0_0, TP0_1 output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T0POL: TP0_0, TP0_1 output polarity control 0: Non-invert 1: Invert This bit controls the polarity of the TP0_0 or TP0_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. T0DPX: TM0 PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. T0CCLR: Select TM0 Counter clear condition 0: TM0 Comparatror P match 1: TM0 Comparatror A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T0CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T0CCLR bit is not used in the PWM Mode.
Bit 3
Bit 1
Bit 0
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Compact Type TM Operating Modes
The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register.
Compare Match Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00B respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place.
Timer/Counter Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
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Counter Value 0x3FF CCRP
Pause Stop
Counter overflow
CCRP=0
TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value
Resume Counter Restart
CCRP > 0
CCRA
Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF
TM O/P Pin
Output pin set to initial Level Low if TnOC=0 Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Output not affected by TnAF flag. Remains High until reset by TnON bit Note TnIO [1:0] = 10 Active High Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function
Compare Match Output Mode -- TnCCLR = 0 Note: 1. With TnCCLR=0, a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge
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Counter Value 0x3FF
Resume
TnCCLR = 1; TnM [1:0] = 00 CCRA > 0 Counter cleared by CCRA value CCRA=0
Stop Counter Restart
CCRA = 0 Counter overflow
CCRA CCRP
Pause
Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF
TnPF not generated Output does not change Output not affected by TnAF flag. Remains High until reset by TnON bit Note TnIO [1:0] = 10 Active High Output select No TnAF flag generated on CCRA overflow
TM O/P Pin
Output pin set to initial Level Low if TnOC=0 Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function
Compare Match Output Mode -- TnCCLR = 1 Note: 1. With TnCCLR=1, a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1
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An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform.
*
CTM, PWM Mode, Edge-aligned Mode, T0DPX=0
001b 128 010b 256 011b 384 100b 512 CCRA 101b 640 110b 768 111b 896 000b 1024
CCRP Period Duty
If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA =128, The CTM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%.
*
CTM, PWM Mode, Edge-aligned Mode, T0DPX=1
001b 010b 011b 100b CCRA 128 256 384 512 640 768 896 1024 101b 110b 111b 000b
CCRP Period Duty
The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value.
Counter Value Counter cleared by CCRP
Pause Resume
TnDPX = 0; TnM [1:0] = 10
Counter Reset when TnON returns high Counter Stop if TnON bit low
CCRP CCRA
Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1
PWM Mode -- TnDPX = 0 Note: 1. Here TnDPX=0 -- Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation
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Counter Value Counter cleared by CCRA
Pause Resume
TnDPX = 1; TnM [1:0] = 10
Counter Reset when TnON returns high Counter Stop if TnON bit low
CCRA CCRP
Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0) PWM Duty Cycle set by CCRP PWM Period set by CCRA PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1
PWM Mode -- TnDPX = 1 Note: 1. Here TnDPX = 1 -- Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation
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Standard Type TM - STM
The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with an external input pin and can drive one or two external output pins.
CTM HT68F13/HT68F14 HT68F15 Name 10-bit STM 3/4 TM No. 1 3/4 TM Input Pin TCK1 3/4 TM Output Pin TP1_0, TP1_1 3/4
Standard TM Operation
At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers.
CCRP
3 - b it C o m p a r a to r P
C o m p a ra to r P M a tc h
T n P F In te rru p t
fS
YS
/4
YS
fS
fH /1 6 fH /6 4 fT B C R e s e rv e d TCKn
000 001 010 011 100 101 110 111 TnO N TnPAU
b7~b9
TnO C TPn_0 TPn_1
1 0 - b it C o u n t- u p C o u n te r
C o u n te r C le a r 1 TnC CLR
0
O u tp u t C o n tro l
P o la r ity C o n tro l
T P n P in In p u t/O u tp u t
b0~b9
TnM 1,TnM 0 T n IO 1 , T n IO 0
TnPO L
1 0 - b it C o m p a r a to r A
C o m p a ra to r A
M a tc h T n IO 1 , T n IO 0
T n A F In te rru p t
TnC K2~TnC K0
CCRA Edge D e te c to r
Standard Type TM Block Diagram
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Standard Type TM Register Description
Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits.
STM Register List - HT68F13/ HT68F14 Name TM1C0 TM1C1 TM1DL TM1DH TM1AL TM1AH Bit7 T1PAU T1M1 D7 3/4 D7 3/4 Bit6 T1CK2 T1M0 D6 3/4 D6 3/4 Bit5 T1CK1 T1IO1 D5 3/4 D5 3/4 Bit4 T1CK0 T1IO0 D4 3/4 D4 3/4 Bit3 T1ON T1OC D3 3/4 D3 3/4 Bit2 T1RP2 T1POL D2 3/4 D2 3/4 Bit1 T1RP1 T1DPX D1 D9 D1 D9 Bit0 T1RP0 T1CCLR D0 D8 D0 D8
10-bit Standard TM Register List TM1C0 Register Bit Name R/W POR Bit 7 7 T1PAU R/W 0 6 T1CK2 R/W 0 5 T1CK1 R/W 0 4 T1CK0 R/W 0 3 T1ON R/W 0 2 T1RP2 R/W 0 1 T1RP1 R/W 0 0 T1RP0 R/W 0
Bit 6~4
Bit 3
T1PAU: TM1 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. T1CK2~T1CK0: Select TM1 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: undefined 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. T1ON: TM1 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T1OC bit, when the T1ON bit changes from low to high.
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Bit 2~0 T1RP2~T1RP0: TM1 CCRP 3-bit register, compared with the TM1 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM1 clocks 001: 128 TM1 clocks 010: 256 TM1 clocks 011: 384 TM1 clocks 100: 512 TM1 clocks 101: 640 TM1 clocks 110: 768 TM1 clocks 111: 896 TM1 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter's highest three bits. The result of this comparison can be selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. TM1C1 Register Bit Name R/W POR Bit 7~6 7 T1M1 R/W 0 6 T1M0 R/W 0 5 T1IO1 R/W 0 4 T1IO0 R/W 0 3 T1OC R/W 0 2 T1POL R/W 0 1 T1DPX R/W 0 0 T1CCLR R/W 0
Bit 5~4
T1M1~T1M0: Select TM1 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1M1 and T1M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. T1IO1~T1IO0: Select TP1_0, TP1_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1_0, TP1_1 01: Input capture at falling edge of TP1_0, TP1_1 10: Input capture at falling/rising edge of TP1_0, TP1_1 11: Input capture disabled Timer/counter Mode: Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T1IO1 and T1IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T1OC bit in the TM1C1 register. Note that the output level requested by the T1IO1 and T1IO0 bits must be different from
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the initial value setup using the T1OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. In the PWM Mode, the T1IO1 and T1IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the T1IO1 and T1IO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T1IO1 and T1IO0 bits are changed when the TM is running Bit 3 T1OC: TP1_0, TP1_1 Output control bit Compare Match Output Mode 0: initial low 1: initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. T1POL: TP1_0, TP1_1 Output polarity Control 0: non-invert 1: invert This bit controls the polarity of the TP1_0 or TP1_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. T1DPX: TM1 PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. T1CCLR: Select TM1 Counter clear condition 0: TM1 Comparatror P match 1: TM1 Comparatror A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T1CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode.
Bit 2
Bit 1
Bit 0
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TM1DL Register Bit Name R/W POR Bit 7~0 7 D7 R 0 6 D6 R 0 5 D5 R 0 4 D4 R 0 3 D3 R 0 2 D2 R 0 1 D1 R 0 0 D0 R 0
TM1DL: TM1 Counter Low Byte Register bit 7~bit 0 TM1 10-bit Counter bit 7~bit 0 TM1DH Register
Bit Name R/W POR Bit 7~2 Bit 1~0
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 3/4 3/4 3/4
3 3/4 3/4 3/4
2 3/4 3/4 3/4
1 D9 R 0
0 D8 R 0
Unimplemented, read as 0 TM1DH: TM1 Counter High Byte Register bit 1~bit 0 TM1 10-bit Counter bit 9~bit 8 TM1AL Register
Bit Name R/W POR Bit 7~0
7 D7 R/W 0
6 D6 R/W 0
5 D5 R/W 0
4 D4 R/W 0
3 D3 R/W 0
2 D2 R/W 0
1 D1 R/W 0
0 D0 R/W 0
TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0 TM1 10-bit CCRA bit 7~bit 0 TM1AH Registe
Bit Name R/W POR Bit 7~2 Bit 1~0
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 3/4 3/4 3/4
3 3/4 3/4 3/4
2 3/4 3/4 3/4
1 D9 R/W 0
0 D8 R/W 0
Unimplemented, read as 0 TM1AH: TM1 CCRA High Byte Register bit 1~bit 0 TM1 10-bit CCRA bit 9~bit 8
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Standard Type TM Operating Modes
The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register.
Compare Match Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to 0.
Counter Value 0x3FF CCRP
Pause Stop
Counter overflow
CCRP=0
TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value
Resume Counter Restart
CCRP > 0
CCRA
Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF
TM O/P Pin
Output pin set to initial Level Low if TnOC=0 Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Output not affected by TnAF flag. Remains High until reset by TnON bit Note TnIO [1:0] = 10 Active High Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function
Compare Match Output Mode -- TnCCLR = 0 Note: 1. With TnCCLR=0 a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to itsinitial state by a TnON bit rising edge
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As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place.
Timer/Counter Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function.
Counter Value 0x3FF
Resume
TnCCLR = 1; TnM [1:0] = 00 CCRA > 0 Counter cleared by CCRA value CCRA=0
Stop Counter Restart
CCRA = 0 Counter overflow
CCRA CCRP
Pause
Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF
TnPF not generated Output does not change Output not affected by TnAF flag. Remains High until reset by TnON bit Note TnIO [1:0] = 10 Active High Output select No TnAF flag generated on CCRA overflow
TM O/P Pin
Output pin set to initial Level Low if TnOC=0 Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function
Compare Match Output Mode -- TnCCLR = 1 Note: 1. With TnCCLR=1 a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. A TnPF flag is not generated when TnCCLR=1
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
PWM Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform.
*
STM, PWM Mode, Edge-aligned Mode, T0DPX=0
001b 128 010b 256 011b 384 100b 512 CCRA 101b 640 110b 768 111b 896 000b 1024
CCRP Period Duty
If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA =128, The STM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%.
*
STM, PWM Mode, Edge-aligned Mode, T0DPX=1
001b 010b 011b 100b CCRA 128 256 384 512 640 768 896 1024 101b 110b 111b 000b
CCRP Period Duty
The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value.
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Counter Value Counter cleared by CCRP
Pause Resume
TnDPX = 0; TnM [1:0] = 10
Counter Reset when TnON returns high Counter Stop if TnON bit low
CCRP CCRA
Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0) PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1
PWM Period set by CCRP
PWM Mode -- TnDPX = 0 Note: 1. Here TnDPX=0 -- Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation
Rev. 1.10
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February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Counter Value Counter cleared by CCRA
Pause Resume
TnDPX = 1; TnM [1:0] = 10
Counter Reset when TnON returns high Counter Stop if TnON bit low
CCRA CCRP
Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0) PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Duty Cycle set by CCRP PWM Period set by CCRA
PWM Mode -- TnDPX = 1 Note: 1. Here TnDPX=1 -- Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation
Single Pulse Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A.
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Com m and S E T "T n O N " or T C K n P in T r a n s itio n S /W L e a d in g E d g e T n O N b it 0(R) 1 T r a ilin g E d g e T n O N b it 1(R) 0 S /W C o m m a n d C L R "T n O N " or C C R A M a tc h C o m p a re
T M n O u tp u t P in P u ls e W id th = C C R A V a lu e
Single Pulse Generation
However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in this Mode.
Counter Value TnM [1:0] = 10 ; TnIO [1:0] = 11
Counter Reset when TnON returns high Pause Resume Counter Stops by software
Counter stopped by CCRA
CCRA CCRP
Time TnON
Software Trigger Cleared by CCRA match Auto. set by TCKn pin Software Trigger Software Trigger
Software Clear
Software Trigger
TCKn pin TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF
No CCRP Interrupts generated TCKn pin Trigger
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0) Pulse Width set by CCRA Output Inverts when TnPOL = 1
Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the TCKn pin or by setting the TnON bit high 4. A TCKn pin active edge will automatically set the TnON bit high 5. In the Single Pulse Mode, TnIO [1:0] must be set to 11 and can not be changed.
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Capture Input Mode
To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPn_0 or TPn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPn_0 or TPn_1 pin, the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the TPn_0 or TPn_1 pin the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs, the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPn_0 or TPn_1 pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPn_0 or TPn_1 pin, however it must be noted that the counter will continue to run. As the TPn_0 or TPn_1 pin is pin shared with other functions, care must be taken if the TM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR and TnDPX bits are not used in this Mode.
Counter Value Counter cleared by CCRP TnM [1:0] = 01
Counter Counter Stop Reset
CCRP YY XX Time TnON TnPAU
Active edge
Resume Pause
TM capture pin TPn_x CCRA Int. Flag TnAF CCRP Int. Flag TnPF CCRA Value TnIO [1:0] Value
00 Rising edge
Active edge
Active edge
XX
YY
XX
YY
01
Falling edge
10
Both edges
11
Disable Capture
Capture Input Mode Note: 1.. TnM [1:0] = 01 and active edge set by the TnIO [1:0] bits 2. A TM Capture input pin active edge transfers the counter value to CCRA 3. TnCCLR bit not used 4. No output function -- TnOC and TnPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero.
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Enhanced Type TM - ETM
The Enhanced Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Enhanced TM can also be controlled with an external input pin and can drive three or four external output pins.
CTM HT68F13/HT68F14 HT68F15 Name 3/4 10-bit ETM TM No. 3/4 1 TM Input Pin 3/4 TCK1 TM Output Pin 3/4 TP1A; TP1B_0, TP1B_1, TP1B_2
Enhanced TM Operation
At its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. There are three internal comparators with the names, Comparator A, Comparator B and Comparator P. These comparators will compare the value in the counter with the CCRA, CCRB and CCRP registers. The CCRP comparator is 3 bits wide whose value is compared with the highest 3 bits in the counter while CCRA and CCRB are 10 bits wide and therefore compared with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Enhanced Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control output pins. All operating setup conditions are selected using relevant internal registers.
CCRP C o m p a ra to r P M a tc h
3 - b it C o m p a r a to r P
T n P F In te rru p t
fS
YS
/4
YS
fS
fH /1 6 fH /6 4 fT B C R e s e rv e d TCKn
000 001 010 011 100 101 110 111
b7~b9
TnAO C
1 0 - b it U p /D o w n C o u n te r
C o u n te r C le a r 0 1 TnC CLR
O u tp u t C o n tro l
P o la r ity C o n tro l
T P n A P in In p u t/O u tp u t
TPnA
TnO N TnPAU
b0~b9
TnAM 1,TnAM 0 T n A IO 1 , T n A IO 0
TnAPO L
TnC K2~TnC K0
1 0 - b it C o m p a ra to r A
C o m p a ra to r A
M a tc h
TnAF In te rru p t
T n A IO 1 , T n A IO 0 CCRA Edge D e te c to r TnBO C T P n B -0 T P n B -1 T P n B -2
1 0 - b it C o m p a ra to r B
C o m p a ra to r B
M a tc h TnBF In te rru p t Edge D e te c to r
O u tp u t C o n tro l
P o la r ity C o n tro l
T P n B P in In p u t/O u tp u t
CCRB
TnBM 1,TnBM 0 T n B IO 1 , T n B IO 0
TnBPO L
T n IO 1 , T n IO 0
Enhanced Type TM Block Diagram
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Enhanced Type TM Register Description
Overall operation of the Enhanced TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRB value. The remaining three registers are control registers which setup the different operating and control modes as well as the three CCRP bits.
Name TM1C0 TM1C1 TM1C2 TM1DL TM1DH TM1AL TM1AH TM1BL TM1BH Bit7 T1PAU T1AM1 T1BM1 D7 3/4 D7 3/4 D7 3/4 Bit6 T1CK2 T1AM0 T1BM0 D6 3/4 D6 3/4 D6 3/4 Bit5 T1CK1 T1AIO1 T1BIO1 D5 3/4 D5 3/4 D5 3/4 Bit4 T1CK0 T1AIO0 T1BIO0 D4 3/4 D4 3/4 D4 3/4 Bit3 T1ON T1AOC T1BOC D3 3/4 D3 3/4 D3 3/4 Bit2 T1RP2 T1APOL T1BPOL D2 3/4 D2 3/4 D2 3/4 Bit1 T1RP1 T1CDN T1PWM1 D1 D9 D1 D9 D1 D9 Bit0 T1RP0 T1CCLR T1PWM0 D0 D8 D0 D8 D0 D8
10-bit Enhanced TM Register List TM1C0 Register Bit Name R/W POR Bit 7 7 T1PAU R/W 0 6 T1CK2 R/W 0 5 T1CK1 R/W 0 4 T1CK0 R/W 0 3 T1ON R/W 0 2 T1RP2 R/W 0 1 T1RP1 R/W 0 0 T1RP0 R/W 0
Bit 6~4
T1PAU: TM1 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. T1CK2~T1CK0: Select TM1 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Undefined 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section.
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Bit 3 T1ON: TM1 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T1OC bit, when the T1ON bit changes from low to high. T1RP2~T1RP0: TM1 CCRP 3-bit register, compared with the TM1 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM1 clocks 001: 128 TM1 clocks 010: 256 TM1 clocks 011: 384 TM1 clocks 100: 512 TM1 clocks 101: 640 TM1 clocks 110: 768 TM1 clocks 111: 896 TM1 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counters highest three bits. The result of this comparison can be selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. TM1C1 Register Bit Name R/W POR Bit 7~6 7 T1AM1 R/W 0 6 T1AM0 R/W 0 5 T1AIO1 R/W 0 4 T1AIO0 R/W 0 3 T1AOC R/W 0 2 T1APOL R/W 0 1 T1CDN R 0 0 T1CCLR R/W 0
Bit 2~0
Bit 5~4
T1AM1~T1AM0: Select TM1 CCRA Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1AM1 and T1AM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. T1AIO1~T1AIO0: Select TP1A output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1A 01: Input capture at falling edge of TP1A 10: Input capture at falling/rising edge of TP1A 11: Input capture disabled
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T1AIO1 and T1AIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T1AOC bit in the TM1C1 register. Note that the output level requested by the T1AIO1 and T1AIO0 bits must be different from the initial value setup using the T1AOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. In the PWM Mode, the T1AIO1 and T1AIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the T1AIO1 and T1AIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T1AIO1 and T1AIO0 bits are changed when the TM is running T1AOC: TP1A Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. T1APOL: TP1A Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP1A output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. T1CDN: TM1 Counter count up or down flag 0: Count up 1: Count down T1CCLR: Select TM1 Counter clear condition 0: TM1 Comparator P match 1: TM1 Comparator A match This bit is used to select the method which clears the counter. Remember that the Enhanced TM contains three comparators, Comparator A, Comparator B and Comparator P, but only Comparator A or Comparator Pan be selected to clear the internal counter. With the T1CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not used in the Single Pulse or Input Capture Mode.
Bit 3
Bit 2
Bit 1
Bit 0
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
TM1C2 Register Bit Name R/W POR Bit 7~6 7 T1BM1 R/W 0 6 T1BM0 R/W 0 5 T1BIO1 R/W 0 4 T1BIO0 R/W 0 3 T1BOC R/W 0 2 T1BPOL R/W 0 1 T1PWM1 R 0 0 T1PWM0 R/W 0
Bit 5~4
T1BM1~T1BM0: Select TM1 CCRB Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1BM1 and T1BM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. T1BIO1~T1BIO0: Select TP1B_0, TP1B_1, TP1B_2 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1B_0, TP1B_1, TP1B_2 01: Input capture at falling edge of TP1B_0, TP1B_1, TP1B_2 10: Input capture at falling/rising edge of TP1B_0, TP1B_1, TP1B_2 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T1BIO1 and T1BIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T1BOC bit in the TM1C2 register. Note that the output level requested by the T1BIO1 and T1BIO0 bits must be different from the initial value setup using the T1BOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. In the PWM Mode, the T1BIO1 and T1BIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the T1BIO1 and T1BIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T1BIO1 and T1BIO0 bits are changed when the TM is running
Rev. 1.10
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February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Bit 3 T1BOC: TP1B_0, TP1B_1, TP1B_2 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. T1BPOL: TP1B_0, TP1B_1, TB1B_2 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP1B_0, TP1B_1, TP1B_2 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. T1PWM1~T1PWM0: Select PWM Mode 00: Edge aligned 01: Centre aligned, compare match on count up 10: Centre aligned, compare match on count down 11: Centre aligned, compare match on count up or down TM1DL Register Bit Name R/W POR Bit 7~0 7 D7 R 0 6 D6 R 0 5 D5 R 0 4 D4 R 0 3 D3 R 0 2 D2 R 0 1 D1 R 0 0 D0 R 0
Bit 2
Bit 1~0
TM1DL: TM1 Counter Low Byte Register bit 7~bit 0 TM1 10-bit Counter bit 7~bit 0 TM1DH Register
Bit Name R/W POR Bit 7~2 Bit 1~0
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 3/4 3/4 3/4
3 3/4 3/4 3/4
2 3/4 3/4 3/4
1 D9 R 0
0 D8 R 0
Unimplemented, read as 0 TM1DH: TM1 Counter High Byte Register bit 1~bit 0 TM1 10-bit Counter bit 9~bit 8 TM1AL Register
Bit Name R/W POR Bit 7~0
7 D7 R/W 0
6 D6 R/W 0
5 D5 R/W 0
4 D4 R/W 0
3 D3 R/W 0
2 D2 R/W 0
1 D1 R/W 0
0 D0 R/W 0
TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0 TM1 10-bit CCRA bit 7~bit 0
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
TM1AH Register Bit Name R/W POR Bit 7~2 Bit 1~0 7 3/4 3/4 3/4 6 3/4 3/4 3/4 5 3/4 3/4 3/4 4 3/4 3/4 3/4 3 3/4 3/4 3/4 2 3/4 3/4 3/4 1 D9 R/W 0 0 D8 R/W 0
Unimplemented, read as 0 TM1AH: TM1 CCRA High Byte Register bit 1~bit 0 TM1 10-bit CCRA bit 9~bit 8 TM1BL Register
Bit Name R/W POR Bit 7 ~ 0
7 D7 R/W 0
6 D6 R/W 0
5 D5 R/W 0
4 D4 R/W 0
3 D3 R/W 0
2 D2 R/W 0
1 D1 R/W 0
0 D0 R/W 0
TM1BL: TM1 CCRB Low Byte Register bit 7~bit 0 TM1 10-bit CCRB bit 7~bit 0
TM1BH Register Bit Name R/W POR Bit 7~2 Bit 1~0 7 3/4 3/4 3/4 6 3/4 3/4 3/4 5 3/4 3/4 3/4 4 3/4 3/4 3/4 3 3/4 3/4 3/4 2 3/4 3/4 3/4 1 D9 R/W 0 0 D8 R/W 0
Unimplemented, read as 0 TM1BH: TM1 CCRB High Byte Register bit 1~bit 0 TM1 10-bit CCRB bit 9 ~ bit 8
Enhanced Type TM Operating Modes
The Enhanced Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnAM1 and TnAM0 bits in the TMnC1, and the TnBM1 and TnBM0 bits in the TMnC2 register.
CCRA CCRA CCRA Single CCRA Input Compare CCRA PWM Timer/Count Pulse Output Capture Match Output Mode er Mode Mode Mode Output Mode O 3/4 3/4 3/4 3/4 3/4 O 3/4 3/4 3/4 3/4 3/4 O 3/4 3/4 3/4 3/4 3/4 O 3/4 3/4 3/4 3/4 3/4 O
ETM Operating Mode
CCRB Compare Match Output Mode CCRB Timer/Counter Mode CCRB PWM Output Mode CCRB Single Pulse Output Mode CCRB Input Capture Mode
O: permitted; 3/4 : not permitted
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Compare Output Mode
To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1/TMnC2 registers should be all cleared to zero. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both the TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated.
Counter Value 0x3FF CCRP
Counter overflow
CCRP=0
TnCCLR = 0; TnAM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value
Resume Pause Stop Counter Restart
CCRP > 0
CCRA
Time TnON TnPAU TnAPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF
TPnA O/P Pin
Output pin set to initial Level Low if TnAOC=0 Output Toggle with TnAF flag Here TnAIO [1:0] = 11 Toggle Output select Output not affected by TnAF flag. Remains High until reset by TnON bit Note TnAIO [1:0] = 10 Active High Output select Output Inverts when TnAPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function
ETM CCRA Compare Match Output Mode -- TnCCLR = 0 Note: 1. With TnCCLR=0 a Comparator P match will clear the counter 2. The TPnA output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge
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As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a TnAF or TnBF interrupt request flag is generated after a compare match occurs from Comparator A or Comparator B. The TnPF interrupt request flag, generated from a compare match from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state is determined by the condition of the TnAIO1 and TnAIO0 bits in the TMnC1 register for ETM CCRA, and the TnBIO1 and TnBIO0 bits in the TMnC2 register for ETM CCRB. The TM output pin can be selected using the TnAIO1, TnAIO0 bits (for the TPnA pin) and TnBIO1, TnBIO0 bits (for the TPnB_0, TPnB_1 or TPnB_2 pins) to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A or a compare match occurs from Comparator B. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnAOC or TnBOC bit for TPnA or TPnB_0, TPnB_1, TPnB_2 output pins. Note that if the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits are zero then no pin change will take place.
Counter Value 0x3FF CCRP
Counter overflow
CCRP=0
TnCCLR = 0; TnBM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value
Resume Pause Stop Counter Restart
CCRP > 0
CCRB
Time TnON TnPAU TnBPOL CCRP Int. Flag TnPF CCRB Int. Flag TnBF
TPnB O/P Pin
Output pin set to initial Level Low if TnBOC=0 Output Toggle with TnBF flag Here TnBIO [1:0] = 11 Toggle Output select Output not affected by TnBF flag. Remains High until reset by TnON bit Note TnBIO [1:0] = 10 Active High Output select Output Inverts when TnBPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function
ETM CCRB Compare Match Output Mode -- TnCCLR = 0 Note: 1. With TnCCLR=0 a Comparator P match will clear the counter 2. The TPnB output pin is controlled only by the TnBF flag 3. The output pin is reset to its initial state by a TnON bit rising edge
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As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when an TnAF or TnBF interrupt request flag is generated after a compare match occurs from Comparator A or Comparator B. The TnPF interrupt request flag, generated from a compare match from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state is determined by the condition of the TnAIO1 and TnAIO0 bits in the TMnC1 register for ETM CCRA, and the TnBIO1 and TnBIO0 bits in the TMnC2 register for ETM CCRB. The TM output pin can be selected using the TnAIO1, TnAIO0 bits (for the TPnA pin) and TnBIO1, TnBIO0 bits (for the TPnB_0, TPnB_1 or TPnB_2 pins) to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A or a compare match occurs from Comparator B. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnAOC or TnBOC bit for TPnA or TPnB_0, TPnB_1, TPnB_2 output pins. Note that if the TnAIO1,TnAIO0 and TnBIO1, TnBIO0 bits are zero then no pin change will take place.
Counter Value 0x3FF
TnCCLR = 1; TnAM [1:0] = 00 CCRA > 0 Counter cleared by CCRA value
Resume
CCRA = 0 Counter overflow CCRA=0
Stop Counter Restart
CCRA CCRP
Pause
Time TnON TnPAU TnAPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF
TnPF not generated Output does not change Output not affected by TnAF flag. Remains High until reset by TnON bit Note TnAIO [1:0] = 10 Active High Output select No TnAF flag generated on CCRA overflow
TPnA O/P Pin
Output pin set to initial Level Low if TnAOC=0 Output Toggle with TnAF flag Here TnAIO [1:0] = 11 Toggle Output select
Output Inverts when TnAPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function
ETM CCRA Compare Match Output Mode -- TnCCLR = 1 Note: 1. With TnCCLR=1 a Comparator A match will clear the counter 2. The TPnA output pin is controlled only by the TnAF flag 3. The TPnA output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1
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Counter Value 0x3FF
Resume
TnCCLR = 1; TnBM [1:0] = 00 CCRA > 0 Counter cleared by CCRA value CCRA=0
Stop Counter Restart
CCRA = 0 Counter overflow
CCRA CCRB
Pause
Time TnON TnPAU TnBPOL CCRA Int. Flag TnAF CCRB Int. Flag TnBF
No TnAF flag generated on CCRA overflow
TPnB O/P Pin
Output pin set to initial Level Low if TnBOC=0 Output Toggle with TnBF flag
Output not affected by TnBF flag. Remains High until reset by TnON bit Note TnBIO [1:0] = 10 Active High Output select
Output Inverts when TnBPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function
Here TnBIO [1:0] = 11 Toggle Output select
ETM CCRB Compare Match Output Mode -- TnCCLR = 1 Note: 1. With TnCCLR=1 a Comparator A match will clear the counter 2. The TPnB output pin is controlled only by the TnBF flag 3. The TPnB output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 Timer/Counter Mode
To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 register should all be set high. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10 respectively and also the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit is used to determine in which way the PWM period is controlled. With the TnCCLR bit set high, the PWM period can be finely controlled using the CCRA registers. In this case the CCRB registers are used to set the PWM duty value (for TPnB output pins). The CCRP bits are not used and TPnA output pin is not used. The PWM output can
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only be generated on the TPnB output pins. With the TnCCLR bit cleared to zero, the PWM period is set using one of the eight values of the three CCRP bits, in multiples of 128. Now both CCRA and CCRB registers can be used to setup different duty cycle values to provide dual PWM outputs on their relative TPnA and TPnB pins. The TnPWM1 and TnPWM0 bits determine the PWM alignment type, which can be either edge or centre type. In edge alignment, the leading edge of the PWM signals will all be generated concurrently when the counter is reset to zero. With all power currents switching on at the same time, this may give rise to problems in higher power applications. In centre alignment the centre of the PWM active signals will occur sequentially, thus reducing the level of simultaneous power switching currents. Interrupt flags, one for each of the CCRA, CCRB and CCRP, will be generated when a compare match occurs from either the Comparator A, Comparator B or Comparator P. The TnAOC and TnBOC bits in the TMnC1 and TMnC2 register are used to select the required polarity of the PWM waveform while the two TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits pairs are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnAPOL and TnBPOL bit are used to reverse the polarity of the PWM output waveform.
*
ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0
001b 128 010b 256 011b 384 100b 512 CCRA CCRB 101b 640 110b 768 111b 896 000b 1024
CCRP Period A Duty B Duty
If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 100b, CCRA = 128 and CCRB = 256, The TP1A PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125kHz, duty = 128/512 = 25%. The TP1B_n PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125kHz, duty = 256/512 = 50%. If the Duty value defined by CCRA or CCRB register is equal to or greater than the Period value, then the PWM output duty is 100%.
*
ETM, PWM Mode, Edge-aligned Mode, TnCCLR=1
1 1 2 2 3 3 511 511 CCRB 512 512 1021 1021 1022 1022 1023 1023
CCRA Period B Duty
*
ETM, PWM Mode, Center-aligned Mode, TnCCLR=0
001b 256 010b 512 011b 768 100b 1024 101b 1280 110b 1536 111b 1792 000b 2046
CCRP Period A Duty B Duty
*
(CCRA2)-1 (CCRB2)-1
ETM, PWM Mode, Center-aligned Mode, TnCCLR=1
1 2 2 4 3 6 511 1022 512 1024 1021 2042 1022 2044 1023 2046
CCRA Period B Duty
(CCRB2)-1
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Counter Value Counter Cleared by CCRP
CCRP CCRA
Pause Resume Counter Restart
TnCCLR = 0; TnAM [1:0] = 10, TnBM [1:0] = 10; TnPWM [1:0] = 00
Stop
CCRB
Time
TnON
TnPAU
TnAPOL CCRA Int. Flag TnAF CCRB Int. Flag TnBF CCRP Int. Flag TnPF TPnA Pin
(TnAOC=1)
Duty Cycle set by CCRA Duty Cycle set by CCRA Duty Cycle set by CCRA Output Inverts when TnAPOL is high
TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Duty Cycle set by CCRB Output controlled by other pin-shared function Output Pin Reset to Initial value
PWM Period set by CCRP
ETM PWM Mode -- Edge Aligned Note: 1. Here TnCCLR=0 therefore CCRP clears counter and determines the PWM period 2. The internal PWM function continues running even when TnAIO [1:0] (or TnBIO [1:0]) = 00 or 01 3. CCRA controls the TPnA PWM duty and CCRB controls the TPnB PWM duty
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Counter Value Counter Cleared by CCRA
CCRA
Resume Counter Restart
TnCCLR = 1; TnBM [1:0] = 10; TnPWM [1:0] = 00
Pause
Stop
CCRB
Time
TnON
TnPAU
TnBPOL CCRP Int. Flag TnPF CCRB Int. Flag TnBF TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Duty Cycle set by CCRB Output controlled by other pin-shared function Output Pin Reset to Initial value Output Inverts when TnBPOL is high
PWM Period set by CCRA
ETM PWM Mode -- Edge Aligned Note: 1. Here TnCCLR=1 therefore CCRA clears the counter and determines the PWM period 2. The internal PWM function continues running even when TnBIO [1:0] = 00 or 01 3. The CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty 4. Here the TM pin control register should not enable the TPnA pin as a TM output pin.
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Counter Value TnCCLR = 0; TnAM [1:0] = 10, TnBM [1:0] = 10; TnPWM [1:0] = 11
Stop Counter Restart
CCRP CCRA CCRB
Resume Pause
Time
TnON TnPAU
TnAPOL CCRA Int. Flag TnAF CCRB Int. Flag TnBF CCRP Int. Flag TnPF TPnA Pin
(TnAOC=1)
Duty Cycle set by CCRA
TPnB Pin
(TnBOC=1)
Output Inverts when TnAPOL is high
TPnB Pin
(TnBOC=0)
Duty Cycle set by CCRB PWM Period set by CCRP Output controlled by Other pin-shared function Output Pin Reset to Initial value
ETM PWM Mode -- Centre Aligned Note: 1. Here TnCCLR=0 therefore CCRP clears the counter and determines the PWM period 2. TnPWM [1:0] =11 therefore the PWM is centre aligned 3. The internal PWM function continues running even when TnAIO [1:0] (or TnBIO [1:0]) = 00 or 01 4. CCRA controls the TPnA PWM duty and CCRB controls the TPnB PWM duty 5. CCRP will generate an interrupt request when the counter decrements to its zero value
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Counter Value
CCRA
Resume Pause Stop
TnCCLR = 1; TnBM [1:0] = 10; TnPWM [1:0] = 11
Counter Restart
CCRB
Time
TnON TnPAU TnBPOL CCRA Int. Flag TnAF CCRB Int. Flag TnBF CCRP Int. Flag TnPF TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Duty Cycle set by CCRB PWM Period set by CCRA Output controlled Output Inverts by other pin-shared when TnBPOL is high function Output Pin Reset to Initial value
ETM PWM Mode -- Centre Aligned Note: 1. Here TnCCLR=1 therefore CCRA clears the counter and determines the PWM period 2. TnPWM [1:0] =11 therefore the PWM is centre aligned 3. The internal PWM function continues running even when TnBIO [1:0] = 00 or 01 4. CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty 5. CCRP will generate an interrupt request when the counter decrements to its zero value
Single Pulse Output Mode
To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10 respectively and also the corresponding TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse TPnA output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. The trigger for the pulse TPnB output leading edge is a compare match from Comparator B, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output of TPnA. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge of TPnA will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge of TPnA and TPnB will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A.
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However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge of TPnA and TPnB. In this way the CCRA value can be used to control the pulse width of TPnA. The CCRA-CCRB value can be used to control the pulse width of TPnB. A compare match from Comparator A and Comparator B will also generate TM interrupts. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR bit is also not used.
Single Pulse Generation
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Counter Value Counter stopped by CCRA TnAM [1:0] = 10, TnBM [1:0] = 10; TnAIO [1:0] = 11, TnBIO [1:0] = 11
Counter Reset when TnON returns high
CCRA
Pause Resume
Counter Stops by software
CCRB Time TnON
Software Trigger Cleared by CCRA match Auto. set by TCKn pin Software Trigger Software Trigger Software Clear Software Trigger
TCKn pin TnPAU TnAPOL TnBPOL CCRB Int. Flag TnBF CCRA Int. Flag TnAF TPnA Pin
(TnAOC=1)
TCKn pin Trigger
TPnA Pin
(TnAOC=0)
Pulse Width set by CCRA Output Inverts when TnAPOL=1
TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Pulse Width set by (CCRA-CCRB)
Output Inverts when TnBPOL=1
Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the TCKn pin or by setting the TnON bit high 4. A TCKn pin active edge will automatically set the TnON bit high 5. In the Single Pulse Mode, TnAIO [1:0] and TnBIO [1:0] must be set to 11 and can not be changed.
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Capture Input Mode
To select this mode bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 registers should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits in the TMnC1 and TMnC2 registers. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins the present value in the counter will be latched into the CCRA and CCRB registers and a TM interrupt generated. Irrespective of what events occur on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits can select the active trigger edge on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins to be a rising edge, falling edge or both edge types. If the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins, however it must be noted that the counter will continue to run.
Counter Value Counter cleared by CCRP TnAM [1:0] = 01
Counter Counter Stop Reset
CCRP YY XX Time TnON TnPAU
Active edge
Resume Pause
TM capture pin TPnA CCRA Int. Flag TnAF CCRP Int. Flag TnPF CCRA Value TnAIO [1:0] Value
00 Rising edge
Active edge
Active edge
XX
YY
XX
YY
01
Falling edge
10
Both edges
11
Disable Capture
ETM CCRA Capture Input Mode Note: 1. TnAM [1:0] = 01 and active edge set by the TnAIO [1:0] bits 2. The TM Capture input pin active edge transfers he counter value to CCRA 3. TnCCLR bit not used 4. No output function -- TnAOC and TnAPOL bits not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero.
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As the TPnA and TPnB_0, TPnB_1, TPnB_2 pins are pin shared with other functions, care must be taken if the TM is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR, TnAOC, TnBOC, TnAPOL and TnBPOL bits are not used in this mode.
Counter Value
Counter cleared by CCRP
TnBM [1:0] = 01
Counter Counter Stop Reset
CCRP YY XX Time TnON TnPAU
Active edge
Resume Pause
TM capture pin TPnB_x CCRB Int. Flag TnBF CCRP Int. Flag TnPF CCRB Value TnBIO [1:0] Value
00 Rising edge
Active edge
Active edge
XX
YY
XX
YY
01
Falling edge
10
Both edges
11
Disable Capture
ETM CCRB Capture Input Mode Note: 1. TnBM [1:0] = 01 and active edge set by the TnBIO [1:0] bits 2. The TM Capture input pin active edge transfers the counter value to CCRB 3. TnCCLR bit not used 4. No output function -- TnBOC and TnBPOL bits not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero.
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Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0 and INT1 pins while the internal interrupts are generated by various internal functions such as the TMs, Time Base, and LVD.
Interrupt Registers
Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. The first is the INTC0~INTC1 registers which setup the primary interrupts, the second is the MFI0~MFI1 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an E for enable/ disable bit or F for request flag.
Function Global INTn Pin Multi-function Time Base LVD Enable Bit EMI INTnE MFnE TBE LVE TnPE TM TnAE TnBE Request Flag 3/4 INTnF MFnF TBF LVF TnPF n = 0 or 1 TnAF TnBF n=1 Notes 3/4 n = 0 or 1 n = 0 or 1 3/4 3/4
Interrupt Register Bit Naming Conventions
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Interrupt Register Contents - HT68F13 Name INTEG INTC0 INTC1 Bit 7 3/4 3/4 LVF 6 3/4 T1PF TBF 5 3/4 INT1F 3/4 4 3/4 INT0F T1AF 3 INT1S1 T1PE LVE 2 INT1S0 INT1E TBE 1 INT0S1 INT0E 3/4 0 INT0S0 EMI T1AE
Interrupt Register Contents - HT68F14 Name INTEG INTC0 INTC1 MFI0 MFI1 Bit 7 3/4 3/4 LVF 3/4 3/4 6 3/4 MF0F TBF 3/4 3/4 5 3/4 INT1F 3/4 T0AF T1AF 4 3/4 INT0F MF1F T0PF T1PF 3 INT1S1 MF0E LVE 3/4 3/4 2 INT1S0 INT1E TBE 3/4 3/4 1 INT0S1 INT0E 3/4 T0AE T1AE 0 INT0S0 EMI MF1E T0PE T1PE
Interrupt Register Contents - HT68F15 Name INTEG INTC0 INTC1 MFI0 MFI1 Bit 7 3/4 3/4 LVF 3/4 3/4 6 3/4 MF0F TBF 3/4 T1BF 5 3/4 INT1F 3/4 T0AF T1AF 4 3/4 INT0F MF1F T0PF T1PF 3 INT1S1 MF0E LVE 3/4 3/4 2 INT1S0 INT1E TBE 3/4 T1BE 1 INT0S1 INT0E 3/4 T0AE T1AE 0 INT0S0 EMI MF1E T0PE T1PE
INTEG Register - HT68F13/HT68F14/HT68F15 Bit Name R/W POR Bit 7~4 Bit 3~2 7 3/4 3/4 3/4 6 3/4 3/4 3/4 5 3/4 3/4 3/4 4 3/4 3/4 3/4 3 INT1S1 R/W 0 2 INT1S0 R/W 0 1 INT0S1 R/W 0 0 INT0S0 R/W 0
Bit 1~0
unimplemented, read as 0 INT1S1, INT1S0: interrupt edge control for INT1 pin 00: disable 01: rising edge 10: falling edge 11: both rising and falling edges INT0S1, INT0S0: interrupt edge control for INT0 pin 00: disable 01: rising edge 10: falling edge 11: both rising and falling edges
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INTC0 Register - HT68F13 Bit Name R/W POR Bit 7 Bit 6 7 3/4 3/4 3/4 6 T1PF R/W 0 5 INT1F R/W 0 4 INT0F R/W 0 3 T1PE R/W 0 2 INT1E R/W 0 1 INT0E R/W 0 0 EMI R/W 0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
unimplemented, read as 0 T1PF: TM1 Comparator P match interrupt request flag 0: no request 1: interrupt request INT1F: INT1 interrupt request flag 0: no request 1: interrupt request INT0F: INT0 interrupt request flag 0: no request 1: interrupt request T1PE: TM1 Comparator P match interrupt control 0: disable 1: enable INT1E: INT1 interrupt control 0: disable 1: enable INT0E: INT0 interrupt control 0: disable 1: enable EMI: Global interrupt control 0: disable 1: enable INTC0 Register - HT68F14/HT68F15 Bit 7 3/4 3/4 3/4 6 MF0F R/W 0 5 INT1F R/W 0 4 INT0F R/W 0 3 MF0E R/W 0 2 INT1E R/W 0 1 INT0E R/W 0 0 EMI R/W 0
Name R/W POR Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
unimplemented, read as 0 MF0F: Multi-function 0 Interrupt request flag 0: no request 1: interrupt request INT1F: INT1 interrupt request flag 0: no request 1: interrupt request INT0F: INT0 interrupt request flag 0: no request 1: interrupt request MF0E: Multi-function 0 Interrupt control 0: disable 1: enable INT1E: INT1 interrupt control 0: disable 1: enable INT0E: INT0 interrupt control 0: disable 1: enable EMI: Global interrupt control 0: disable 1: enable
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
INTC1 Register - HT68F13 Bit Name R/W POR Bit 7 7 LVF R/W 0 6 TBF R/W 0 5 3/4 3/4 3/4 4 T1AF R/W 0 3 LVE R/W 0 2 TBE R/W 0 1 3/4 3/4 3/4 0 T1AE R/W 0
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
LVF: LVD Interrupt request flag 0: no request 1: interrupt request TBF: Time Base Interrupt request flag 0: no request 1: interrupt request unimplemented, read as 0 T1AF: TM1 Comparator A match Interrupt request flag 0: no request 1: interrupt request LVE: LVD interrupt control 0: disable 1: enable TBE: Time Base interrupt control 0: disable 1: enable unimplemented, read as 0 T1AE: TM1 Comparator A match Interrupt control 0: disable 1: enable INTC1 Register - HT68F14/HT68F15
Bit Name R/W POR Bit 7
7 LVF R/W 0
6 TBF R/W 0
5 3/4 3/4 3/4
4 MF1F R/W 0
3 LVE R/W 0
2 TBE R/W 0
1 3/4 3/4 3/4
0 MF1E R/W 0
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
LVF: LVD Interrupt request flag 0: no request 1: interrupt request TBF: Time Base Interrupt request flag 0: no request 1: interrupt request unimplemented, read as 0 MF1F: Multi-function 1 Interrupt request flag 0: no request 1: interrupt request LVE: LVD interrupt control 0: disable 1: enable TBE: Time Base interrupt control 0: disable 1: enable unimplemented, read as 0 MF1E: Multi-function 1 Interrupt control 0: disable 1: enable
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MFI0 Register - HT68F14/HT68F15 Bit Name R/W POR Bit 7~6 Bit 5 7 3/4 3/4 3/4 6 3/4 3/4 3/4 5 T0AF R/W 0 4 T0PF R/W 0 3 3/4 3/4 3/4 2 3/4 3/4 3/4 1 T0AE R/W 0 0 T0PE R/W 0
Bit 4
unimplemented, read as 0 T0AF: TM0 Comparator A match interrupt request flag 0: no request 1: interrupt request T0PF: TM0 Comparator P match interrupt request flag 0: no request 1: interrupt request unimplemented, read as 0 T0AE: TM0 Comparator A match interrupt control 0: disable 1: enable T0PE: TM0 Comparator P match interrupt control 0: disable 1: enable MFI1 Register - HT68F14
Bit 3~2 Bit 1
Bit 0
Bit Name R/W POR Bit 7~6 Bit 5
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 T1AF R/W 0
4 T1PF R/W 0
3 3/4 3/4 3/4
2 3/4 3/4 3/4
1 T1AE R/W 0
0 T1PE R/W 0
Bit 4
unimplemented, read as 0 T1AF: TM1 Comparator A match interrupt request flag 0: no request 1: interrupt request T1PF: TM1 Comparator P match interrupt request flag 0: no request 1: interrupt request unimplemented, read as 0 T1AE: TM1 Comparator A match interrupt control 0: disable 1: enable T1PE: TM1 Comparator P match interrupt control 0: disable 1: enable
Bit 3~2 Bit 1
Bit 0
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MFI1 Register - HT68F15 Bit Name R/W POR Bit 7 Bit 6 7 3/4 3/4 3/4 6 T1BF R/W 0 5 T1AF R/W 0 4 T1PF R/W 0 3 3/4 3/4 3/4 2 T1BE R/W 0 1 T1AE R/W 0 0 T1PE R/W 0
Bit 5
Bit 4
unimplemented, read as 0 T1BF: TM1 Comparator B match Interrupt request flag 0: no request 1: interrupt request T1AF: TM1 Comparator A match interrupt request flag 0: no request 1: interrupt request T1PF: TM1 Comparator P match interrupt request flag 0: no request 1: interrupt request unimplemented, read as 0 T1BE: TM1 Comparator B match interrupt control 0: disable 1: enable T1AE: TM1 Comparator A match interrupt control 0: disable 1: enable T1PE: TM1 Comparator P match interrupt control 0: disable 1: enable
Bit 3 Bit 2
Bit 1
Bit 0
Interrupt Operation
When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A or Comparator B match, etc., the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded.
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If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode.
xxF xxE
Legend Request Flag, auto reset in ISR Enable Bits Request Flags INT0F INT1F T1PF T1AF TBF LVF
EMI auto disabled in ISR Master Enable EMI EMI EMI EMI EMI EMI
Interrupt Name INT0 Pin INT1 Pin TM1 P TM1 A Time Base LVD
Enable Bits INT0E INT1E T1PE T1AE TBE LVE
Vector 04H 08H 0CH 10H 18H 1CH
Priority High
Low
Interrupt Structure - HT68F13
xxF xxF xxE
Legend Request Flag, no auto reset in ISR Request Flag, auto reset in ISR Enable Bits Interrupt Name INT0 Pin T0PE T0AE T1PE T1AE INT1 Pin M. Funct. 0 M. Funct. 1 Time Base LVD Request Flags INT0F INT1F MF0F MF1F TBF LVF
EMI auto disabled in ISR
Enable Bits INT0E INT1E MF0E MF1E TBE LVE
Master Enable EMI EMI EMI EMI EMI EMI
Vector 04H 08H 0CH 10H 18H 1CH
Priority High
TM0 P TM0 A TM1 P TM1 A
T0PF T0AF T1PF T1AF
Interrupts contained within Multi-Function Interrupts
Low
Interrupt Structure - HT68F14
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HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Legend xxF xxF xxE Request Flag, no auto reset in ISR Request Flag, auto reset in ISR Enable Bits Interrupt Name INT0 Pin T0PE T0AE T1PE T1AE T1BE LVD Interrupts contained within Multi-Function Interrupts LVF LVE EMI 1CH Low INT1 Pin M. Funct. 0 M. Funct. 1 Time Base Request Flags INT0F INT1F MF0F MF1F TBF Enable Bits INT0E INT1E MF0E MF1E TBE Master Enable EMI EMI EMI EMI EMI Vector 04H 08H 0CH 10H 18H Priority High EMI auto disabled in ISR
TM0 P TM0 A TM1 P TM1 A TM1 B
T0PF T0AF T1PF T1AF T1BF
Interrupt Structure - HT68F15
External Interrupt
The external interrupts are controlled by signal transitions on the pins INT0~INT1. An external interrupt request will take place when the external interrupt request flags, INT0F~INT1F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT1E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F~INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function.
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Multi-function Interrupt
Within these devices there are up to six Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MF0F~MF1F are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related Multi-Function request flag, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts, will not be automatically reset and must be manually reset by the application program.
Time Base Interrupts
The function of the Time Base Interrupt is to provide regular time signal in the form of an internal interrupt. It is controlled by the overflow signal from the respective timer function. When this happens, the respective interrupt request flags TBF will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit EMI and Time Base enable bit TBE must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag TBF will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources originate from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several different sources, as shown in the System Operating Mode section.
fS /4
BC
YS
fT
MUX
fT
B
D iv id e b y 2
12
~2
15
T im e B a s e In te r r u p t
MUX
TB1~TB0
Time Base Interrupt
Note: The fTBC is from the LIRC oscillator.
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TBC Register Bit Name R/W POR Bit 7 7 TBON R/W 0 6 TBCK R/W 0 5 TB1 R/W 1 4 TB0 R/W 1 3 3/4 3/4 3/4 2 3/4 3/4 3/4 1 3/4 3/4 3/4 0 3/4 3/4 3/4
Bit 6
Bit 5~4
TBON: Time Base control 0: disable 1: enable TBCK: Time Base clock fTB selection 0: fTBC 1: fSYS/4 TB1~TB0: Select Time Base Time-out Period 00: 4096/fTB 01: 8192/fTB 10: 16384/fTB 11: 32768/fTB unimplemented, read as 0
Bit 3~0
LVD Interrupt
The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. A LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program.
TM Interrupts
The Compact and Standard Type TMs have two interrupts each, while the Enhanced Type TM has three interrupts. All of the TM interrupts are contained within the Multi-function Interrupts in these devices except HT68F13. For each of the Compact and Standard Type TMs there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and TnAE. For the Enhanced Type TM there are three interrupt request flags TnPF, TnAF and TnBF and three enable bits TnPE, TnAE and TnBE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P, A or B match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program.
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Interrupt Wake-up Function
Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function.
Programming Considerations
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MF0F~MF1F, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the CALL instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts.
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Power Down Mode and Wake-up
Entering the IDLE or SLEEP Mode
There is only one way for the device to enter the SLEEP or IDLE Mode and that is to execute the HALT instruction in the application program. When this instruction is executed, the following will occur:
* * *
The system clock will be stopped and the application program will stop at the HALT instruction. The Data Memory contents and registers will maintain their present condition. The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock source and the WDT is enabled. The WDT will stop if its clock source originates from the system clock. The I/O ports will maintain their present condition. In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared.
* *
Standby Current Considerations
As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the LIRC oscillator.
Wake-up
After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows:
* * * *
An external reset An external falling edge on Port A A system interrupt A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the HALT instruction.
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If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the HALT instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled.
Low Voltage Detector - LVD
Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal.
LVD Register
The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications.
LVDC Register Bit Name R/W POR Bit 7~6 Bit 5 7 3/4 3/4 3/4 6 3/4 3/4 3/4 5 LVDO R 0 4 LVDEN R/W 0 3 3/4 3/4 3/4 2 VLVD2 R/W 0 1 VLVD1 R/W 0 0 VLVD0 R/W 0
Bit
unimplemented, read as 0 LVDO: LVD Output Flag 0: no low voltage detect 1: low voltage detect LVDEN: low voltage detector control 0: disable 1: enable unimplemented, read as 0 VLVD2 ~ VLVD0: select LVD voltage 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.4V
Bit 3 Bit 2~0
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LVD Operation
The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.4V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions.
VDD V LVDEN LVDO tL
LVD
VDS
LVD Operation
The Low Voltage Detector also has its own interrupt which is contained within one of the Multi-function interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode.
SCOM Function for LCD
The devices have the capability of driving external LCD panels. The common pins for LCD driving, SCOM0~ SCOM3, are pin shared with certain pin on the PC0~PC1 and PB6 ~ PB7 pins. The LCD signals (COM and SEG) are generated using the application program.
LCD Operation
An external LCD panel can be driven using this device by configuring the PC0~PC1 or PB6 ~ PB7 pins as common pins and using other output ports lines as segment pins. The LCD driver function is controlled using the SCOMC register which in addition to controlling the overall on/off function also controls the bias voltage setup function. This enables the LCD COM driver to generate the necessary VDD/2 voltage levels for LCD 1/2 bias operation.
V
DD
SCOM V
DD
o p e r a tin g c u r r e n t SC O M 0~ SCOM3
/2
CO M nEN SCOMEN
LCD COM Bias
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The SCOMEN bit in the SCOMC register is the overall master control for the LCD driver; however this bit is used in conjunction with the COMnEN bits to select which Port C pins are used for LCD driving. Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation.
SCOMEN 0 1 1 COMnEN X 0 1 Pin Function I/O I/O SCOMn Output Control O/P Level 0 or 1 0 or 1 VDD/2
LCD Bias Control
The LCD COM driver enables a range of selections to be provided to suit the requirement of the LCD panel which is being used. The bias resistor choice is implemented using the ISEL1 and ISEL0 bits in the SCOMC register.
SCOMC Register Bit Name R/W POR Bit 7 7 D7 R/W 0 6 ISEL1 R/W 0 5 ISEL0 R/W 0 4 SCOMEN R/W 0 3 COM3EN R/W 0 2 COM2EN R/W 0 1 COM1EN R/W 0 0 COM0EN R/W 0
Bit 6~5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved Bit 0: Correct level - bit must be reset to zero for correct operation 1: Unpredictable operation - bit must not be set high ISEL1, ISEL0: ISEL1 ~ ISEL0: Select SCOM typical bias current (VDD=5V) 00: 25mA 01: 50mA 10: 100mA 11: 200mA SCOMEN: SCOM module control 0: disable 1: enable COM3EN: GPIO or SCOM3 selection 0: GPIO 1: SCOM3 COM2EN: GPIO or SCOM2 selection 0: GPIO 1: SCOM2 COM1EN: GPIO or SCOM1 selection 0: GPIO 1: SCOM1 COM0EN: GPIO or SCOM0 selection 0: GPIO 1: SCOM0
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Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table.
No. Oscillator Options 1 2 High Speed System Oscillator Selection - fH: HXT, ERC, HIRC High Speed Internal RC Frequency Selection: 4MHz, 8MHz or 12MHz Options
Reset Pin Options 3 Pin function: RES or PB3
Watchdog Options 4 5 6 Watchdog Timer: enable or disable Watchdog Timer clock source Selection: fSUB or fSYS/4 Note: The fSUB and the fTBC clock source are the LIRC oscillator. CLRWDT instructions: 1 or 2 instructions
LVR Options 7 8 LVR function: enable or disable LVR voltage: 2.10V, 2.55V, 3.15V or 4.2V
Application Circuits
0 .0 1 m F * * V
DD
VDD 10kW ~ 100kW 300W * RES Reset C ir c u it
0 .1 m F
1N4148* 0 .1 ~ 1 m F
PA4~PA7
PB0,PB4~PB7 PC 0~PC 7 PD 0~PD 1
VSS
OSC C ir c u it S e e O s c illa to r S e c tio n
OSC1 OSC2
Note:
* It is recommended that this component is added for added ESD protection. ** It is recommended that this component is added in environments where power line noise is significant.
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Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified.
Logical and Rotate Operations
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations.
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Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections.
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Instruction Set Summary
The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Description Cycles Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z
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Mnemonic Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Description Cycles Flag Affected
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z
Description Operation Affected flag(s)
ADCM A,[m]
Description Operation Affected flag(s)
ADD A,[m]
Description Operation Affected flag(s)
ADD A,x
Description Operation Affected flag(s)
ADDM A,[m]
Description Operation Affected flag(s)
AND A,[m]
Description Operation Affected flag(s)
AND A,x
Description Operation Affected flag(s)
ANDM A,[m]
Description Operation Affected flag(s)
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CALL addr
Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Description
Operation Affected flag(s)
CLR [m]
Description Operation Affected flag(s)
CLR [m].i
Description Operation Affected flag(s)
CLR WDT
Description Operation
Affected flag(s)
CLR WDT1
Description
Operation
Affected flag(s)
CLR WDT2
Description
Operation
Affected flag(s)
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CPL [m]
Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Description Operation Affected flag(s)
CPLA [m]
Description
Operation Affected flag(s)
DAA [m]
Description
Operation
Affected flag(s)
DEC [m]
Description Operation Affected flag(s)
DECA [m]
Description Operation Affected flag(s)
HALT
Description
Operation Affected flag(s)
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INC [m]
Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Description Operation Affected flag(s)
INCA [m]
Description Operation Affected flag(s)
JMP addr
Description
Operation Affected flag(s)
MOV A,[m]
Description Operation Affected flag(s)
MOV A,x
Description Operation Affected flag(s)
MOV [m],A
Description Operation Affected flag(s)
NOP
Description Operation Affected flag(s)
OR A,[m]
Description Operation Affected flag(s)
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OR A,x
Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Description Operation Affected flag(s)
ORM A,[m]
Description Operation Affected flag(s)
RET
Description Operation Affected flag(s)
RET A,x
Description Operation Affected flag(s)
RETI
Description
Operation Affected flag(s)
RL [m]
Description Operation Affected flag(s)
RLA [m]
Description
Operation Affected flag(s)
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RLC [m]
Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Description Operation
Affected flag(s)
RLCA [m]
Description
Operation
Affected flag(s)
RR [m]
Description Operation Affected flag(s)
RRA [m]
Description
Operation Affected flag(s)
RRC [m]
Description Operation
Affected flag(s)
RRCA [m]
Description
Operation
Affected flag(s)
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SBC A,[m]
Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Description
Operation Affected flag(s)
SBCM A,[m]
Description
Operation Affected flag(s)
SDZ [m]
Description
Operation Affected flag(s)
SDZA [m]
Description
Operation Affected flag(s)
SET [m]
Description Operation Affected flag(s)
SET [m].i
Description Operation Affected flag(s)
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SIZ [m]
Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Description
Operation Affected flag(s)
SIZA [m]
Description
Operation Affected flag(s)
SNZ [m].i
Description
Operation Affected flag(s)
SUB A,[m]
Description
Operation Affected flag(s)
SUBM A,[m]
Description
Operation Affected flag(s)
SUB A,x
Description
Operation Affected flag(s)
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SWAP [m]
Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Description Operation Affected flag(s)
SWAPA [m]
Description
Operation Affected flag(s)
SZ [m]
Description
Operation Affected flag(s)
SZA [m]
Description
Operation Affected flag(s)
SZ [m].i
Description
Operation Affected flag(s)
TABRDC [m]
Description Operation Affected flag(s)
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TABRDL [m]
Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
Description Operation Affected flag(s)
XOR A,[m]
Description Operation Affected flag(s)
XORM A,[m]
Description Operation Affected flag(s)
XOR A,x
Description Operation Affected flag(s)
Rev. 1.10
136
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Package Information
16-pin DIP (300mil) Outline Dimensions
A B
16 1 8 9
A B
16 1 8 9
H C D E F G I D E F G C
H
I
Fig1. Full Lead Packages
Fig2. 1/2 Lead Packages
MS-001d (see fig1) Symbol A B C D E F G H I Dimensions in inch Min. 0.780 0.240 0.115 0.115 0.014 0.045 3/4 0.300 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 0.100 3/4 3/4 Dimensions in mm Min. 19.81 6.10 2.92 2.92 0.36 1.14 3/4 7.62 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 2.54 3/4 3/4 Max. 22.35 7.11 4.95 3.81 0.56 1.78 3/4 8.26 10.92 Max. 0.880 0.280 0.195 0.150 0.022 0.070 3/4 0.325 0.430
Symbol A B C D E F G H I
Rev. 1.10
137
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
MS-001d (see fig2) Symbol A B C D E F G H I Dimensions in inch Min. 0.735 0.240 0.115 0.115 0.014 0.045 3/4 0.300 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 0.100 3/4 3/4 Dimensions in mm Min. 18.67 6.10 2.92 2.92 0.36 1.14 3/4 7.62 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 2.54 3/4 3/4 Max. 19.69 7.11 4.95 3.81 0.56 1.78 3/4 8.26 10.92 Max. 0.775 0.280 0.195 0.150 0.022 0.070 3/4 0.325 0.430
Symbol A B C D E F G H I
Rev. 1.10
138
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
MO-095a (see fig2) Symbol A B C D E F G H I Dimensions in inch Min. 0.745 0.275 0.120 0.110 0.014 0.045 3/4 0.300 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 0.100 3/4 3/4 Dimensions in mm Min. 18.92 6.99 3.05 2.79 0.36 1.14 3/4 7.62 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 2.54 3/4 3/4 Max. 19.94 7.49 3.81 3.81 0.56 1.52 3/4 8.26 10.92 Max. 0.785 0.295 0.150 0.150 0.022 0.060 3/4 0.325 0.430
Symbol A B C D E F G H I
Rev. 1.10
139
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
16-pin NSOP (150mil) Outline Dimensions
A 1
16 9 8 C C'
B
D E F
G H
a
MS-012 Symbol A B C C D E F G H a Symbol A B C C D E F G H a Dimensions in inch Min. 0.228 0.150 0.012 0.386 3/4 3/4 0.004 0.016 0.007 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.050 3/4 3/4 3/4 3/4 Dimensions in mm Min. 5.79 3.81 0.30 9.80 3/4 3/4 0.10 0.41 0.18 0 Nom. 3/4 3/4 3/4 3/4 3/4 1.27 3/4 3/4 3/4 3/4 Max. 6.20 3.99 0.51 10.21 1.75 3/4 0.25 1.27 0.25 8 Max. 0.244 0.157 0.020 0.402 0.069 3/4 0.010 0.050 0.010 8
Rev. 1.10
140
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
16-pin SSOP (150mil) Outline Dimensions
16 A
9 B
1 8 C C' D E
G H
F
a
Symbol A B C C D E F G H a Symbol A B C C D E F G H a
Dimensions in inch Min. 0.228 0.150 0.008 0.189 0.054 3/4 0.004 0.022 0.007 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.025 3/4 3/4 3/4 3/4 Dimensions in mm Min. 5.79 3.81 0.20 4.80 1.37 3/4 0.10 0.56 0.18 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.64 3/4 3/4 3/4 3/4 Max. 6.20 3.99 0.30 5.00 1.52 3/4 0.25 0.71 0.25 8 Max. 0.244 0.157 0.012 0.197 0.060 3/4 0.010 0.028 0.010 8
Rev. 1.10
141
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
20-pin DIP (300mil) Outline Dimensions
A
A
11 10 1
B
20
B
1
20
11 10
H C D E F G I
E D F G C
H
I
Fig1. Full Lead Packages
Fig2. 1/2 Lead Packages
MS-001d (see fig1) Symbol A B C D E F G H I Dimensions in inch Min. 0.980 0.240 0.115 0.115 0.014 0.045 3/4 0.300 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 0.100 3/4 0.430 Dimensions in mm Min. 24.89 6.10 2.92 2.92 0.36 1.14 3/4 7.62 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 2.54 3/4 10.92 Max. 26.92 7.11 4.95 3.81 0.56 1.78 3/4 8.26 3/4 Max. 1.060 0.280 0.195 0.150 0.022 0.070 3/4 0.325 3/4
Symbol A B C D E F G H I
Rev. 1.10
142
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
MO-095a (see fig2) Symbol A B C D E F G H I Dimensions in inch Min. 0.945 0.275 0.120 0.110 0.014 0.045 3/4 0.300 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 0.100 3/4 0.430 Dimensions in mm Min. 24.00 6.99 3.05 2.79 0.36 1.14 3/4 7.62 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 2.54 3/4 10.92 Max. 25.02 7.49 3.81 3.81 0.56 1.52 3/4 8.26 3/4 Max. 0.985 0.295 0.150 0.150 0.022 0.060 3/4 0.325 3/4
Symbol A B C D E F G H I
Rev. 1.10
143
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
20-pin SOP (300mil) Outline Dimensions
20
A
11
B
1
C C' D E
10
G H F
a
MS-013 Symbol A B C C D E F G H a Symbol A B C C D E F G H a Dimensions in inch Min. 0.393 0.256 0.012 0.496 3/4 3/4 0.004 0.016 0.008 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.050 3/4 3/4 3/4 3/4 Dimensions in mm Min. 9.98 6.50 0.30 12.60 3/4 3/4 0.10 0.41 0.20 0 Nom. 3/4 3/4 3/4 3/4 3/4 1.27 3/4 3/4 3/4 3/4 Max. 10.64 7.62 0.51 13.00 2.64 3/4 0.30 1.27 0.33 8 Max. 0.419 0.300 0.020 0.512 0.104 3/4 0.012 0.050 0.013 8
Rev. 1.10
144
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
20-pin SSOP (150mil) Outline Dimensions
20
A
11
B
1
C C' D E
10
G H
F
a
Symbol A B C C D E F G H a Symbol A B C C D E F G H a
Dimensions in inch Min. 0.228 0.150 0.008 0.335 0.049 3/4 0.004 0.015 0.007 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.025 3/4 3/4 3/4 3/4 Dimensions in mm Min. 5.79 3.81 0.20 8.51 1.24 3/4 0.10 0.38 0.18 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.64 3/4 3/4 3/4 3/4 Max. 6.20 4.01 0.30 8.81 1.65 3/4 0.25 1.27 0.25 8 Max. 0.244 0.158 0.012 0.347 0.065 3/4 0.010 0.050 0.010 8
Rev. 1.10
145
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
24-pin SKDIP (300mil) Outline Dimensions
A
A
13 12 1 24
24 13 12 1
B
B
H C D E F G I
D E F C G
H
I
Fig1. Full Lead Packages MS-001d (see fig1) Symbol A B C D E F G H I
Fig2. 1/2 Lead Packages
Dimensions in inch Min. 1.230 0.240 0.115 0.115 0.014 0.045 3/4 0.300 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 0.100 3/4 0.430 Dimensions in mm Min. 31.24 6.10 2.92 2.92 0.36 1.14 3/4 7.62 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 2.54 3/4 10.92 Max. 32.51 7.11 4.95 3.81 0.56 1.78 3/4 8.26 3/4 Max. 1.280 0.280 0.195 0.150 0.022 0.070 3/4 0.325 3/4
Symbol A B C D E F G H I
Rev. 1.10
146
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
MS-001d (see fig2) Symbol A B C D E F G H I Dimensions in inch Min. 1.160 0.240 0.115 0.115 0.014 0.045 3/4 0.300 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 0.100 3/4 0.430 Dimensions in mm Min. 29.46 6.10 2.92 2.92 0.36 1.14 3/4 7.62 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 2.54 3/4 10.92 Max. 30.35 7.11 4.95 3.81 0.56 1.78 3/4 8.26 3/4 Max. 1.195 0.280 0.195 0.150 0.022 0.070 3/4 0.325 3/4
Symbol A B C D E F G H I
Rev. 1.10
147
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
MO-095a (see fig2) Symbol A B C D E F G H I Dimensions in inch Min. 1.145 0.275 0.120 0.110 0.014 0.045 3/4 0.300 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 0.100 3/4 0.430 Dimensions in mm Min. 29.08 6.99 3.05 2.79 0.36 1.14 3/4 7.62 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 2.54 3/4 10.92 Max. 30.10 7.49 3.81 3.81 0.56 1.52 3/4 8.26 3/4 Max. 1.185 0.295 0.150 0.150 0.022 0.060 3/4 0.325 3/4
Symbol A B C D E F G H I
Rev. 1.10
148
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
24-pin SOP (300mil) Outline Dimensions
24 A
13 B
1 C C' D E
12
G H F
a
MS-013 Symbol A B C C D E F G H a Symbol A B C C D E F G H a Dimensions in inch Min. 0.393 0.256 0.012 0.598 3/4 3/4 0.004 0.016 0.008 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.050 3/4 3/4 3/4 3/4 Dimensions in mm Min. 9.98 6.50 0.30 15.19 3/4 3/4 0.10 0.41 0.20 0 Nom. 3/4 3/4 3/4 3/4 3/4 1.27 3/4 3/4 3/4 3/4 Max. 10.64 7.62 0.51 15.57 2.64 3/4 0.30 1.27 0.33 8 Max. 0.419 0.300 0.020 0.613 0.104 3/4 0.012 0.050 0.013 8
Rev. 1.10
149
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
24-pin SSOP (150mil) Outline Dimensions
24 A
13 B
1 C C' D E
12
G H F
a
Symbol A B C C D E F G H a Symbol A B C C D E F G H a
Dimensions in inch Min. 0.228 0.150 0.008 0.335 0.054 3/4 0.004 0.022 0.007 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.025 3/4 3/4 3/4 3/4 Dimensions in mm Min. 5.79 3.81 0.20 8.51 1.37 3/4 0.10 0.56 0.18 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.64 3/4 3/4 3/4 3/4 Max. 6.20 3.99 0.30 8.79 1.52 3/4 0.25 0.71 0.25 8 Max. 0.244 0.157 0.012 0.346 0.060 3/4 0.010 0.028 0.010 8
Rev. 1.10
150
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
28-pin SKDIP (300mil) Outline Dimensions
A B
28 1 15 14
H C D E F G I
Symbol A B C D E F G H I
Dimensions in inch Min. 1.375 0.278 0.125 0.125 0.016 0.050 3/4 0.295 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 0.100 3/4 0.375 Dimensions in mm Min. 34.93 7.06 3.18 3.18 0.41 1.27 3/4 7.49 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 2.54 3/4 9.53 Max. 35.43 7.57 3.43 3.68 0.51 1.78 3/4 8.00 3/4 Max. 1.395 0.298 0.135 0.145 0.020 0.070 3/4 0.315 3/4
Symbol A B C D E F G H I
Rev. 1.10
151
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
28-pin SOP (300mil) Outline Dimensions
28 A
15 B
1 C C' D E
14
G H F
a
MS-013 Symbol A B C C D E F G H a Symbol A B C C D E F G H a Dimensions in inch Min. 0.393 0.256 0.012 0.697 3/4 3/4 0.004 0.016 0.008 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.050 3/4 3/4 3/4 3/4 Dimensions in mm Min. 9.98 6.50 0.30 17.70 3/4 3/4 0.10 0.41 0.20 0 Nom. 3/4 3/4 3/4 3/4 3/4 1.27 3/4 3/4 3/4 3/4 Max. 10.64 7.62 0.51 18.11 2.64 3/4 0.30 1.27 0.33 8 Max. 0.419 0.300 0.020 0.713 0.104 3/4 0.012 0.050 0.013 8
Rev. 1.10
152
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
28-pin SSOP (150mil) Outline Dimensions
28 A 1 C C' D E
15 B 14
G H a F
Symbol A B C C D E F G H a Symbol A B C C D E F G H a
Dimensions in inch Min. 0.228 0.150 0.008 0.386 0.054 3/4 0.004 0.022 0.007 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.025 3/4 3/4 3/4 3/4 Dimensions in mm Min. 5.79 3.81 0.20 9.80 1.37 3/4 0.10 0.56 0.18 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.64 3/4 3/4 3/4 3/4 Max. 6.20 3.99 0.30 10.01 1.52 3/4 0.25 0.71 0.25 8 Max. 0.244 0.157 0.012 0.394 0.060 3/4 0.010 0.028 0.010 8
Rev. 1.10
153
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Reel Dimensions
T2 D
A
B
C
T1
SOP 16N (150mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0
+0.5/-0.2
2.00.5 16.8
+0.3/-0.2
22.20.2
SOP 20W, SOP 24W, SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0
+0.5/-0.2
2.00.5 24.8
+0.3/-0.2
30.20.2
Rev. 1.10
154
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
SSOP 16S Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0
+0.5/-0.2
2.00.5 12.8
+0.3/-0.2
18.20.2
SSOP 20S (150mil), SSOP 24S (150mil), SSOP 28S (150mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0
+0.5/-0.2
2.00.5 16.8
+0.3/-0.2
22.20.2
SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.00.1 13.0
+0.5/-0.2
2.00.5 32.2
+0.3/-0.2
38.20.2
Rev. 1.10
155
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Carrier Tape Dimensions
D
E F W C
P0
P1
t
B0
D1
P
A0
K0
R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e .
SOP 16N (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 16.00.3 8.00.1 1.750.1 7.50.1 1.55 1.50
+0.10/-0.00 +0.25/-0.00
4.00.1 2.00.1 6.50.1 10.30.1 2.10.1 0.300.05 13.30.1
Rev. 1.10
156
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
SOP 20W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width SOP 24W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.1 11.50.1 1.55 1.50
+0.10/-0.00 +0.25/-0.00
Description Carrier Tape Width
Dimensions in mm 24.0
+0.3/-0.1
12.00.1 1.750.10 11.50.1 1.5 1.50
+0.1/-0.0 +0.25/-0.00
4.00.1 2.00.1 10.80.1 13.30.1 3.20.1 0.300.05 21.30.1
4.00.1 2.00.1 10.90.1 15.90.1 3.10.1 0.350.05 21.30.1
Rev. 1.10
157
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.10 11.50.1 1.5 1.50
+0.1/-0.0 +0.25/-0.00
4.00.1 2.00.1 10.850.10 18.340.10 2.970.10 0.350.01 21.30.1
SSOP 16S Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 12.0
+0.3/-0.1
8.00.1 1.750.10 5.50.1 1.550.10 1.50
+0.25/-0.00
4.00.1 2.00.1 6.40.1 5.20.1 2.10.1 0.300.05 9.30.1
Rev. 1.10
158
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
SSOP 20S (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 16.0
+0.3/-0.1
8.00.1 1.750.10 7.50.1 1.5 1.50
+0.1/-0.0 +0.25/-0.00
4.00.1 2.00.1 6.50.1 9.00.1 2.30.1 0.300.05 13.30.1
SSOP 24S (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 16.0+0.3/-0.1 8.00.1 1.750.10 7.50.1 1.5+0.1/-0.0 1.50+0.25/-0.00 4.00.1 2.00.1 6.50.1 9.50.1 2.10.1 0.300.05 13.30.1
Rev. 1.10
159
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
SSOP 28S (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 16.00.3 8.00.1 1.750.1 7.50.1 1.55 1.50
+0.10/-0.00 +0.25/-0.00
4.00.1 2.00.1 6.50.1 10.30.1 2.10.1 0.300.05 13.30.1
Rev. 1.10
160
February 9, 2011
HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2011 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
161
February 9, 2011

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